Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A complementary metal-oxide-semiconductor field-effect transistor (CMOS) device includes a first source/drain (S/D) region and a second S/D region different from the first S/D region. A first epitaxy film formed of a first semiconductor material is on the first S/D region. A second epitaxy film formed of a second semiconductor material is on the second S/D region. The CMOS device further includes first and second S/D contact stacks. The first S/D contact stack includes a first contact trench liner having a first inner side wall extending from a first base portion to an upper surface of the first S/D contact stack. The second S/D contact stack includes a second contact trench liner having a second inner side wall extending from a second base portion to an upper surface of the second S/D contact stack. The first inner sidewall directly contacts the second inner sidewall.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.