Abstract: Fine lines (approximately 3 microns or less) are patternable on conductive materials by electromachining techniques. These micro-techniques differ from conventional electromachining in that the linewidth is primarily determined by the characteristics of the electric field rather than the electrode geometry.

Abstract: Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.

Abstract: A method for changing Josephson device parameters, e.g., the critical current of a Josephson junction. The method comprises incorporating doping material into the device, or part of the device, followed by a light anneal. Exemplary dopants include In, Sn, Sb, Te, Bi, Hg, Mg, Li, Cd, Na and Ta, with In, Sn, and Sb being preferred dopants for changing the critical current of a Josephson junction having a Pb-containing counter electrode. The dopant can be incorporated into the device by in-diffusion after deposition onto the surface, by ion implantation, or by any other convenient method. The amount of dopant required is typically small. For example, deposition of a Sn layer of 0.05 nm effective thickness onto the 200 nm thick Pb-Sb(1.5 wt. %) counter electrode of a cross-type Josephson junction, and annealing at 80.degree. C. for about 3 hours, resulted in an increase in the critical current of the junction by a factor of about 2.5.

Abstract: A superconductive circuit is described for diverting bias current to an output line in response to magnetic field control means. A first plurality of branches containing magnetically switchable Josephson junction gates are connected in parallel, and a second plurality of the same gates, less than or equal in number to the first plurality, are actuated essentially simultaneously by the control means. As a consequence, high-gain, high-speed operation is made possible.

Abstract: Described is a DC powered flip-flop logic or memory element (i.e., circuit) which comprises two Josephson junction gates J.sub.1 and J.sub.2 which operate individually in the latching mode. In one logic state, the gate J.sub.1 is at V.sub.1 =O while J.sub.2 is at V.sub.2 .noteq.O. In the other logic state, the roles of the two junctions are reversed. The two junctions are interconnected by a passive network such that the switching of J.sub.2, say, from V.sub.2 =O to V.sub.2 .noteq.O induces a current-voltage transient on J.sub.1 which returns it to V.sub.1 =O, and conversely.

Abstract: A current-switched gate is described which comprises two Josephson tunnel junctions and a small resistor in a triangular loop. Directly combined bias and control currents flow through one junction in the zero-voltage state, causing the switching. The second junction and the resistor provide isolation between input and output after switching. Switching speeds of a few tens of picoseconds and the microwatt power dissipation are attained. Latching as well as nonlatching schemes and memory circuits are described.

Abstract: A DC powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the DC bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V=O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed.

Abstract: Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon career, and depositing the gold on the silicon dioxide layer.