Abstract: Game surface systems configured to display a game sheet on a play surface. The game surface systems include a first module configured to support and protect the game sheet. The first module includes a back member and a cover sheet. The back member abuts the rear surface of the game sheet and is disposed between the game sheet and the play surface. The cover sheet abuts the display face of the game sheet and covers the game sheet. The game sheet includes a display face facing away from the play surface and a rear face facing the play surface. The cover sheet is coupled to the back member. In some examples, the game surface system includes a frame. In certain examples, the game surface system includes a transition module and a transition sheet.

Abstract: Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.

Abstract: A system includes a data path that provides a data signal at a first frequency corresponding to a first clock signal. A strobe generator generates a strobe signal at the first frequency. The strobe signal is synchronized with the data signal based on a second clock signal having a second frequency that is different from the first frequency.

Abstract: One disclosed embodiment may comprise a system to change a data window. The system may comprise a plurality of registers. Each of the plurality of registers is operative, when activated, to receive data from a bi-directional data bus at a respective input. Each of the plurality of registers is activated in a predetermined sequence to latch a respective portion of the data from the bi-directional data bus so that each respective portion of the data has a longer data window at an output of each of the plurality of registers than at the respective input of each of the plurality of registers.

Abstract: Reading and writing data from a plurality of memory devices. A code word having a plurality of bits is partitioned into nibbles. Adjacent nibbles are stored on a common physical medium. The failure of the common physical medium results in errors in adjacent nibbles of a reconstructed code word.

Abstract: A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.

Abstract: A system includes a data path that provides a data signal at a first frequency corresponding to a first clock signal. A strobe generator generates a strobe signal at the first frequency. The strobe signal is synchronized with the data signal based on a second clock signal having a second frequency that is different from the first frequency.

Abstract: Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The bits in the adjacent bit pair domain are processed by an error correction unit sequentially or in parallel, and then recombined to be written into memory or transmitted to a requestor.

Abstract: Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The adjacent bit pair domain data is transmitted over a bus having a plurality of data paths, such that data bits associated with a given memory device are transmitted over a same data path.