Patents by Inventor Theodore C. Moore

Theodore C. Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for detecting presence of residual polishing slurry subsequent to polishing of a semiconductor wafer
    Patent number: 6716364
    Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Newell E. Chiesl, III, Gregory L. Burns, Theodore C. Moore
  • Method and apparatus for detecting presence of residual polishing slurry subsequent to polishing of a semiconductor wafer
    Patent number: 6375791
    Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 23, 2002
    Assignee: LSI Logic Corporation
    Inventors: Newell E. Chiesl, III, Gregory L. Burns, Theodore C. Moore
  • Method for improved gate oxide integrity on bulk silicon
    Patent number: 6096625
    Abstract: The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: August 1, 2000
    Assignee: LSI Logic Corporation
    Inventors: David W. Daniel, Theodore C. Moore, Crystal J. Hass