Patents by Inventor Theodore C Waldron, III

Theodore C Waldron, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6269367
    Abstract: An improved system and method of automating the identification, remediation and verification of computer program code fragments which have no specific search criteria using an iterative dynamic self propagating global symbol table. Computer code is input and then decomposed into predefined table entries. This is used to verify that all of the source code is present and to provide forward and backward linking to related code fragments containing various levels of dynamically modified confidence factors. Global computer program changes can then be made regardless of the initial state of the code fragment or number of redefinition's in a swap-by-propagation fashion. Remediations are logged to provide verification data and to insure complete testing.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: July 31, 2001
    Assignee: MigraTEC, Inc.
    Inventors: Sheldon H. Travis, Jeffrey D. Clignett, William A. Fahle, Jr., Lance P. Johnston, Theodore C Waldron, III
  • Patent number: 6021425
    Abstract: The invention provides a system and method of enhancing efficiency in a data processing system having a processor, a memory, and a multitasking operating system for managing the processor and the memory. A normal and an expedited scheduling path are provided for scheduling tasks on the processor. The tasks are each assigned a priority for execution on the processor. A queue is provided for the placement of tasks ready for execution. Upon entry into the ready-to-run queue, the execution priority of the new task is compared to the execution priority of the executing task. Responsive to the new task holding a higher execution priority or to absence of an executing task, the expedited scheduling path is invoked. Otherwise the normal scheduling path is invoked.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: February 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: Theodore C. Waldron, III, Paul P. Giangarra, Khoa D. Huynh, John G. Tyler, Scott L. Winters
  • Patent number: 5428789
    Abstract: A method in a computer system providing user control over application completion performance and recovering lost computational cycles incurred while running pooling and non-pooling applications concurrently in a priority preemptive operating system. The method and apparatus of the present invention includes identifying the various priority levels in a priority preemptive operating system and providing an automated method for selecting said levels. After the user selection is completed, a scan is conducted to ensure that the selected level will execute prior to starting the application. If the user selected level is too low to execute, a minimum priority level is automatically determined to ensure that the application can execute without delay. The resulting priority is then continuously visually displayed to inform the user of each applications execution eligibility.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: June 27, 1995
    Inventor: Theodore C. Waldron, III
  • Patent number: 5386561
    Abstract: A priority preemptive, time distribution operating system operating in accordance with the method of the present invention provides enhanced efficiency in operation of a data processing system having a central processing unit, a computer memory and an auxiliary memory. The operating system manages the central processing unit, the computer memory and the auxiliary memory where a plurality of processes are presented for execution on the central processing unit by: ordering the processes for execution; allocating a predetermined time slice for execution of a process from the ordering; executing a first current process in the ordering on the central processing unit for the predetermined time slice; responsive to occurrence of a storage access operation during execution of the first current process, allocating a supplemental time slice to the current process for execution; and continuing execution of the current process for the supplemental time slice.
    Type: Grant
    Filed: March 31, 1992
    Date of Patent: January 31, 1995
    Assignee: International Business Machines Corporation
    Inventors: Khoa D. Huynh, Charles M. Norcutt, Jr., Theodore C. Waldron, III
  • Patent number: 5335332
    Abstract: A method and system for enhancing operating system efficiency in a data processing system by ensuring alignment of stack memory at a multi-byte boundary such that multi-byte data fetch operations may be utilized to efficiently retrieve data from the stack memory. At each invocation of an operating system procedure from an application within a data processing system, a stack memory pointer is examined to determine if stack memory contents including passed parameters and local variables to be allocated onto the stack memory will be aligned at a multi-byte boundary. In response to a prospective nonalignment of local variables, the operating system procedure is recursively invoked with an additional "dummy" parameter, such that stack memory contents will be aligned at a multi-byte boundary. Thereafter, the operating system will automatically align data within the stack memory at a multi-byte boundary so that the data may be efficiently stored and retrieved utilizing multi-byte data operations.
    Type: Grant
    Filed: December 24, 1991
    Date of Patent: August 2, 1994
    Assignee: International Business Machines Corporation
    Inventors: Kenneth W. Christopher, Jr., Virginia M. Roarabaugh, Theodore C. Waldron, III
  • Patent number: 5301312
    Abstract: A method in a computer system for monitoring time intervals during which external interrupts are inhibited within the computer system in a selected program being run on the computer system. The method and apparatus of the present invention includes identifying a first plurality of instructions, capable of blocking external interrupts and identifying a second plurality of instructions, capable of unblocking external interrupts. After identifying these instructions, a unique benign fault is inserted proximate to selected ones of the first plurality of instructions and selected ones of the second plurality of instructions to produce a special version program. The special version program is then run in the computer system. Faults which occur during the running of the special version program and associated external interrupt-blocking times are monitored.
    Type: Grant
    Filed: August 21, 1991
    Date of Patent: April 5, 1994
    Assignee: International Business Machines Corporation
    Inventors: Kenneth W. Christopher, Jr., Khoa D. Huynh, Virginia M. Roarabaugh, Theodore C. Waldron, III