Patents by Inventor Theodore Doll

Theodore Doll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6952055
    Abstract: The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: October 4, 2005
    Assignee: California Institute of Technology
    Inventors: Axel Scherer, Theodore Doll, Victor Fuenzalida
  • Patent number: 6613241
    Abstract: The invention is a method of introducing porous membranes into MEMS elements by supporting the membranes by frames to form an heterostructure. This is achieved by attaching to a structured or porous substrate one or more monolithically fabricated frames and membranes. Having membranes disposed on frames enables them to be batch processed and facilitates separation, handling and mounting within MEMS or nanofluidic systems. Applications include, but are not limited to, filters for gases or liquids, electron transmissive windows and scanning electron microscopy (SEM) accessible arrays of nanotest tubes containing liquid phases and other sample states. The invention includes the apparatus made by the method.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 2, 2003
    Assignee: California Insitute of Technology
    Inventors: Axel Scherer, Theodore Doll, Michael Hochberg
  • Patent number: 6461528
    Abstract: Lateral pores in a thin metal film as well as fabricating branching and expanding ore arrays can be fabricated by a method of growing long pores laterally underneath a ask by use of stress compliant masks or varying the anodization voltage. Applications range from use with scanning electron microscope (SEM-compatible single molecule probe stations), to nanowire fixtures and to the use with a “pixelating, nonscanning” near field optical microscope (NOM). Pores are defined by conventional anodization vertically into the underlying membrane of preporous material through any overlying masking layers. The general solution is to utilize mechanically stable masks that withstand the stress during anodization and counteract the pore formation stress to lead to good pore ordering and directed growth. Multilayer masks are well suited for this. With a composition of materials having different elastic properties, tensile stress can be matched to counteract compressive stress caused by porous material growth.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: October 8, 2002
    Assignee: California Institute of Technology
    Inventors: Axel Scherer, Theodore Doll, Thomas Hoffman
  • Publication number: 20020068369
    Abstract: The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described.
    Type: Application
    Filed: August 31, 2001
    Publication date: June 6, 2002
    Inventors: Axel Scherer, Theodore Doll, V. Fuenzalida
  • Patent number: 6350623
    Abstract: The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: February 26, 2002
    Assignee: California Institute of Technology
    Inventors: Axel Scherer, Theodore Doll, V. Fuenzalida