Patents by Inventor Theodore Doros

Theodore Doros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7289198
    Abstract: A method of process variation compensation in step-and-scan lithography which comprises estimating a magnitude of a process error over a full imaged substrate surface and applying error correction during scan exposure over the full imaged substrate surface is provided in the disclosed embodiments.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventors: Alexander Starikov, Theodore Doros
  • Patent number: 7262070
    Abstract: Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick and thin regions of materials. The weight-compensating/tuning layer includes narrow and wide regions corresponding to the thick and thin regions, respectively.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Theodore Doros, Krishna Seshan
  • Publication number: 20070139140
    Abstract: Multiple FBARs may be manufactured on a single wafer and later diced. Ideally, all devices formed in a wafer would have the same resonance frequency. However, due to manufacturing variances, the frequency response of the FBAR devices may vary slightly across the wafer. An RF map may be created to determine zones over the wafer where FBARs in that zone all vary from a target frequency by a similar degree. A tuning layer may be deposited over the wafer. Lithographically patterned features to the tuning layer based on the zones identified by the RF map may be used to correct the FBARs to a target resonance frequency with the FBARs still intact on the wafer.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: Valluri Rao, Theodore Doros, Qing Ma, Krishna Seshan, Li-Peng Wang
  • Patent number: 7006208
    Abstract: In an embodiment in accordance with the present invention, methods for dynamic detection and correction of focus and tilt variations that occur during a specific product layer exposure is by focus and tilt pre-compensation during wafer exposure. The method provides two spaced apart paths that provide both defocus and tilt measurements. A reference plane is defined by using three reference areas or fields. The data is fitted, using least squares or max/min error, to a “plane”, that is, to straight equidistant lines, the deviation from “plane” is computed as error from a set of straight equidistant lines. Lateral displacements of each band into focus error is converted using the formula: ?Z=?X*?.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Alexander Starikov, Theodore Doros
  • Publication number: 20050094132
    Abstract: A method of process variation compensation in step-and-scan lithography which comprises estimating a magnitude of a process error over a full imaged substrate surface and applying error correction during scan exposure over the full imaged substrate surface is provided in the disclosed embodiments.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 5, 2005
    Inventors: Alexander Starikov, Theodore Doros
  • Publication number: 20050070119
    Abstract: Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick and thin regions of materials. The weight-compensating/tuning layer includes narrow and wide regions corresponding to the thick and thin regions, respectively.
    Type: Application
    Filed: September 29, 2003
    Publication date: March 31, 2005
    Inventors: Theodore Doros, Krishna Seshan
  • Publication number: 20040130689
    Abstract: In an embodiment in accordance with the present invention, methods for dynamic detection and correction of focus and tilt variations that occur during a specific product layer exposure is by focus and tilt pre-compensation during wafer exposure. The method provides two spaced apart paths that provide both defocus and tilt measurements. A reference plane is defined by using three reference areas or fields. The data is fitted, using least squares or max/min error, to a “plane”, that is, to straight equidistant lines, the deviation from “plane” is computed as error from a set of straight equidistant lines. Lateral displacements of each band into focus error is converted using the formula: &Dgr;Z=&Dgr;X*&thgr;.
    Type: Application
    Filed: January 7, 2003
    Publication date: July 8, 2004
    Inventors: Alexander Starikov, Theodore Doros