Abstract: One or more domains are independently clocked with separate clocks. Each clock is an asynchronous stop/start clock implementing a self-tuning clocking methodology. Domain circuit speed is monitored and the clock adjusted to tune the domain to run at near maximum speed. Inter-domain data transfers are performed by a four-way handshaking method. In effect the clock period of the respective clocks during the data transfer becomes the slower period of the two domains' clock periods. An inter-domain arbiter is implemented at each domain for deciding which domain's request is to be granted during an immediate clock period. Data input to a domain is tracked to determine when data is present. When no data is present, the domain's clock is stopped.

Abstract: A radix-16 divider, generally including two improved radix-4 dividers cascaded combinatorially, also utilizes improved overlapping quotient bit selection, together with concurrent quotient bit selection and rounding techniques, to produce four bits of quotient per divider cycle with reduced hardware requirements.

Abstract: A radix-16 divider, generally comprising two improved radix-4 dividers cascaded combinatorially, also utilizes improved overlapping quotient bit selection, together with concurrent quotient bit selection and rounding techniques, to produce four bits of quotient per divider cycle with reduced hardware requirements.