Abstract: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.

Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

Abstract: The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a common active region of a circuit, and a test structure for testing one or more functionally separate transistors located within a common active region. The method for testing the electrical property, among other steps, includes providing a pair of functionally separate transistors (110) located within a common active region, and biasing a terminal (135) between the pair (110) relative to gates (125, 155) of the pair (110) and terminals (130, 160) outlying the pair (110) to obtain a leakage current associated with the pair (110).

Abstract: The present invention provides a body bias coordinator for use with a transistor employing a body region. In one embodiment, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. These embodiments improve transistor active and passive performance, permit smaller transistor sizing and reduce leakage current.

Abstract: One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second state. A charge storage device is coupled to maintain the node at a first voltage according to an amount of stored charge. A write assist system is connected between the node and a second voltage. The write assist network is configured, when the node is selected, to discharge the charge storage device and to pull the node from the first voltage to a discharge voltage that is outside a range defined by the first voltage and the second voltage to facilitate setting the latch system to another of the first state and the second state.

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract: The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.

Abstract: A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage, (4) a low voltage power supply configured to supply a low supply voltage, (5) bit line precharge circuitry configured to precharge at least one of the bit lines to a first voltage and (6) standby circuitry configured to maintain a voltage of the at least one bit line at at least a second voltage, the second voltage being lower than the first voltage and higher than the low supply voltage.

Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

Abstract: A static random-access memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) a row of SRAM cells coupled to a word line and a power source configured to vary in voltage to enable the row of SRAM cells to operate in a retain-till-accessed (RTA) mode and (2) a word line driver coupled to the power source and configured to drive the word line.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.

Abstract: An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.

Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

Abstract: An SRAM array and a dummy cell row structure is discussed that permits an SRAM array to be divided into segments isolated by a row pattern of dummy cells. The dummy cell structure avoids the use of special OPC conditions at the power supply line and block boundaries by providing a continuous cell array at the lower cell patterning levels in an area efficient implementation. In one implementation, the SRAM array comprises a first and second array block each comprising an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

Abstract: A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word line driver coupled to word lines of the SRAM array and configured to operate at a word line driver voltage and (2) a bit line precharge circuit coupled to bit lines of the SRAM array and configured to precharge the bit lines to a precharge voltage substantially lower than the word line driver voltage.

Abstract: Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810) overlying the semiconductor device (800), then the resist layer thickness (810y) is reduced (trimmed) to a reduced thickness (860y) by using a subsequent post-development dry or wet resist-reduction etch process (630, 730). The etch process (630, 730) also increases corner rounding (860r), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (228, 328, 860). The pocket shadow reduction may be accomplished by first forming (610, 710) the relatively thick resist layer (810) overlying the semiconductor device (400, 800).

Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

Abstract: According to one embodiment, a method for patterning a set of features for a semiconductor device includes providing a mask including a substrate and at least one pair of first and second main features disposed on a substrate. The method also includes positioning the mask over a layer of light-sensitive material, and exposing the mask to a light source. The mask also includes at least one sub-resolution feature connecting the first and second main features.

Abstract: A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also placed a plurality of times (606, 608, 610) in a second array. The second array is placed adjacent and offset from the first array by an offset distance (O2).