Abstract: A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.