Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract: Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Abstract: An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG.

Abstract: An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306 and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG.