Abstract: A data collection system. A data input form receives data, and a message queue receives the data from the data input form, and temporarily manages the data until the data collection system can process the data. A temporary data storage temporarily stores the data received by the message queue while waiting for the data collection system to process the data. A transaction manager receives the data from the message queue and processes the data. A data logger logs the processing transactions of the transaction manager. A data loader receives the data from the transaction manager and prepares the data for storage. A data storage device receives the data from the data loader.

Abstract: A method for marking a wafer that is cut from a boule. A surface of the boule is marked with an encoded marking that extends completely along a distance of the boule that is used for cutting wafers. The encoded marking is disposed substantially parallel to a length axis of the boule. The wafer is cut from the boule from within the distance, such that the encoded marking along the surface of the boule is disposed at a peripheral edge of the wafer. The encoded marking contains information in regard to the wafer.

Abstract: A method for determining an up time of a multi-component tool having discrete elements, where the up time determination is based upon different processes that are to be accomplished in the multi-component tool. The discrete elements of the multi-component tool and the different processes to be accomplished in the multi-component tool are identified. Different tool states for the multi-component tool are determined by setting element states for each of the discrete elements of the multi-component tool. A first possible element state indicates that the discrete element is functional, and a second possible element state indicates that the discrete element is nonfunctional. Possible combinations of the element states of the discrete elements are identified as the different tool states of the multi-component tool.

Abstract: A computerized engineering database feedback system provides special processing instructions for processing materials in a production process, and provides historical information related to the materials processed according to the special processing instructions. The system includes a request entry device through which requesting personnel may input special processing information indicating a way to process the materials differently from a normal way of processing of the materials. An instruction processing device receives the special processing information and generates the special-processing instructions based thereon. A process station device receives the special-processing instructions, and presents the special-processing instructions to material-processing personnel.

Abstract: A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).

Abstract: A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444).

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structure, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 --SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: Disclosed is a seal which provides effective hermetic sealing of insulated metallic feedthroughs in metallic containers. The device has particular applicability in the fabrication of pressurized metal/gas battery cells such as those used in spacecraft. A conductive terminus protrudes through a metallic vessel which may be pressurized. It is desired to maintain electrical separation between the terminus and the wall of the vessel by means of a dielectric, which is compressed between the terminus and a metallic boss to provide a hermetic seal. The compressive force is applied radially outwardly by means of drawing a nondeformable pin through a hollow cylindrical barrel constituting the terminus, thereby slightly deforming the barrel and grossly deforming the dielectric. The pin may be either pulled out of the barrel from within the vessel or pushed into the barrel from outside the vessel, but in each case force is applied radially outwardly in a gradual, relatively frictionless fashion.

Abstract: A new structure for a pressurized metal-gas battery is presented, with emphasis upon reducing weight and volume. Thus, the battery is particularly suitable for spacecraft applications. Positive and negative terminals are moved away from the center axis of the terminating ellipsoidal domes of a cylindrically shaped pressure vessel, thus permitting smaller size and saving weight while providing torsional support to the electrode stack. A center rod and end plates are fabricated of an insulative, chemically resistant material having a high strength-to-weight ratio, and provide both axial and radial support for the electrode stack while permitting expansion and contraction of the pressure vessel independently of the stack.

Abstract: Disclosed is a battery cell having positive and negative terminals penetrating the same end of the cell, and equalized internal resistance through all paths connecting electrode modules with the terminals. The equalized resistances insure uniform aging of electrode pairs, thus maximizing the life of the battery. A single equalizing busbar is inserted between the equalized terminal, which can be either the negative or the positive terminal, and that end of the equalized busbar remote from the terminaled end of the cell. The length and linear resistance increment of the equalizing busbar are independent of corresponding parameters for the equalized and non-equalized busbars. The resistance increment between any two adjacent electrode connections along each of the equalized and non-equalized busbars must be the same. A simple way to satisfy this condition is to make the length and linear resistance increment of the equalized and non-equalized busbars substantially equal.

Abstract: Disclosed is a seal which provides effective hermetic sealing of insulated metallic feedthroughs in metallic containers. The device has particular applicability in the fabrication of pressurized metal/gas battery cells such as those used in spacecraft. A conductive terminus protrudes through a metallic vessel which may be pressurized. It is desired to maintain electrical separation between the terminus and the wall of the vessel by means of a dielectric, which is compressed between the terminus and a metallic boss to provide a hermetic seal. The compressive force is applied radially outwardly by means of drawing a nondeformable pin through a hollow cylindrical barrel constituting the terminus, thereby slightly deforming the barrel and grossly deforming the dielectric. The pin may be either pulled out of the barrel from within the vessel or pushed into the barrel from outside the vessel, but in each case force is applied radially outwardly in a gradual, relatively frictionless fashion.