Abstract: The computer system architecture utilizes the ability to actively force a ghost line state in management of a split instruction and operand cache associated with an instruction unit with respect to a secondary system integrity cache tag store separately managed by a system controller. The split instruction and operand cache and the system controller tag store permit the management of multiple copies (line-pairs) of a memory line by storing address tag line pair state information with respect to each memory line present in the split-cache to allow determinations of whether and where the respective memory line pair members reside upon access of any one member. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

Abstract: A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system.

Abstract: In a multiprocessor system with an interleaved memory, predicted busy terms for interleaves of the main store being accessed are sent to each processor in the system, so that they will not waste pipe flows making requests to the busy interleaves. The predicted busy term is lowered before access to the interleaves is complete, to allow for the latency between the time the processor sets up the request and the time the main store system receives it. Contention occurs when several processors request access to the same interleave of main store. To detect deadlocks, a counter for each processor keeps track of the number of consecutive requests from that processor which have been rejected. Once the number reaches a threshold for a first processor, its counter initiates a state machine which inhibits other processors from making requests to the main store until the first processor is successful in gaining access.

Abstract: A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.

Abstract: Access control to a high speed data buffer in a data processing machine is bypassed in order to enhance the speed of access of data which must be retrieved from a large capacity main storage facility without requiring additional circuitry in the data processing machine. Access control normally requires an entire line of data to be present in a cache before allowing a read to a portion of the line. When lines are moved in to the cache, only sub-line increments are loaded at a time. Thus, when a line is being moved in from a main store to the cache, the increment that satisfies a pending request for access is transferred first. The access control is overridden to allow access to the increment before the balance of the line is transferred.