Patents by Inventor Theodore Sidney Moise

Theodore Sidney Moise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Enhancement of properties of thin film ferroelectric materials
    Patent number: 8778774
    Abstract: Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignees: University of Florida Research Foundation, Inc., Texas Instruments Incorporated
    Inventors: Toshikazu Nishida, Antonio Guillermo Acosta, John Anthony Rodriguez, Theodore Sidney Moise
  • ENHANCEMENT OF PROPERTIES OF THIN FILM FERROELECTRIC MATERIALS
    Publication number: 20130078742
    Abstract: Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicants: Texas Instruments Incorporated, University of Florida Research Foundation, Incorporated
    Inventors: TOSHIKAZU NISHIDA, Antonio Guillermo Acosta, John Anthony Rodriguez, Theodore Sidney Moise