Patents by Inventor Theodore Van Duzer

Theodore Van Duzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Internally shunted Josephson junction device
    Patent number: 6734454
    Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9° K having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: May 11, 2004
    Assignees: The Regents of the University of California, The Arizona Board of Regents
    Inventors: Theodore Van Duzer, Xiaoxan Meng, Nathan Newman, Lei Yu, Anupama Bhat Kaul
  • Internally shunted Josephson junction device
    Publication number: 20030038286
    Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9°°K. having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 27, 2003
    Applicant: The Regents of the University of California
    Inventors: Theodore Van Duzer, Xiaoxan Meng, Nathan Newman, Lei Yu, Anupama Bhat Kaul
  • High-temperature superconducting josephson devices having a barrier layer of a doped, cubic crystalline, conductive oxide material
    Patent number: 5627139
    Abstract: A HTSC Josephson device wherein the barrier layer is a cubic, conductive material.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: May 6, 1997
    Assignee: The Regents of the University of California
    Inventors: David K. Chin, Theodore Van Duzer
  • Devices comprised of discrete high-temperature superconductor chips disposed on a surface
    Patent number: 5215959
    Abstract: A structure having a surface exposed to electromagnetic radiation in the microwave or millimeter-wave spectrum wherein discrete elements including a high-temperature superconducting film formed on a substrate are disposed on the surface.
    Type: Grant
    Filed: May 18, 1992
    Date of Patent: June 1, 1993
    Assignee: University of California, Berkeley
    Inventor: Theodore Van Duzer