Abstract: Disclosed is an improved approach to implement artificial neural networks. According to some approaches, an advanced neural network is implemented using an internet-of-things methodology, in which a large number of ordinary items having RFID technology are utilized as the vast infrastructure of a neural network. In one approach, the artificial iotons are constructed using a wireless terminal, such as mobile phones, tablets, laptops and WiFi base units that becomes associated with RFID tags. These artificial iotons forms connections with other iotons using wireless technology. An ioton and method of use therefore are also provided, in which the ioton is participated into primary and shareable resources for improved access management to a remote device when forming a distributed processing network, such as a neural network.

Abstract: Disclosed is an improved approach to implement artificial neural networks. According to some approaches, an advanced neural network is implemented using an internet-of-things methodology, in which a large number of ordinary items having RFID technology are utilized as the vast infrastructure of a neural network.

Abstract: Disclosed is an improved approach to implement artificial neural networks. According to some approaches, an advanced neural network is implemented using an internet-of-things methodology, in which a large number of ordinary items having RFID technology are utilized as the vast infrastructure of a neural network.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: Fibrous composite comprising a plurality of carbon nanotubes; and a silica-containing moiety having one of the structures: (SiO)3Si—(CH2)n—NR1R2) or (SiO)3Si—(CH2)n—NCO; where n is from 1 to 6, and R1 and R2 are each independently H, CH3, or C2H5.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: A carbon microtube comprising a hollow, substantially tubular structure having a porous wall, wherein the microtube has a diameter of from about 10 ?m to about 150 ?m, and a density of less than 20 mg/cm3. Also described is a carbon microtube, having a diameter of at least 10 ?m and comprising a hollow, substantially tubular structure having a porous wall, wherein the porous wall comprises a plurality of voids, said voids substantially parallel to the length of the microtube, and defined by an inner surface, an outer surface, and a shared surface separating two adjacent voids.

Abstract: Fibrous composite comprising a plurality of carbon nanotubes; and a silica-containing moiety having one of the structures: (SiO)3Si—(CH2)n—NR1R2) or (SiO)3Si—(CH2)n—NCO; where n is from 1 to 6, and R1 and R2 are each independently H, CH3, or C2H5.

Abstract: A carbon microtube comprising a hollow, substantially tubular structure having a porous wall, wherein the microtube has a diameter of from about 10 ?m to about 150 ?m, and a density of less than 20 mg/cm3. Also described is a carbon microtube, having a diameter of at least 10 ?m and comprising a hollow, substantially tubular structure having a porous wall, wherein the porous wall comprises a plurality of voids, said voids substantially parallel to the length of the microtube, and defined by an inner surface, an outer surface, and a shared surface separating two adjacent voids.

Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A pseudo-spin valve for memory applications, such as magnetoresistive random access memory (MRAM), and methods for fabricating the same, are disclosed. Advantageously, memory devices with the advantageous pseudo-spin valve configuration can be fabricated without cobalt-iron and without anti-ferromagnetic layers, thereby promoting switching repeatability.

Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resisitve memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.

Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising two pinned magnetic layers on one side of a free magnetic layer. The pinned magnetic layers are formed with anti-parallel magnetization orientations such that a net magnetic moment of the two layers is substantially zero. The influence of pinned magnetic layers on free magnetic layer magnetization orientations is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.