Patents by Inventor Theodoros A. Antonakopoulos
Theodoros A. Antonakopoulos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9773549Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: GrantFiled: January 9, 2017Date of Patent: September 26, 2017Assignee: International Business Machines CorporationInventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Publication number: 20170117040Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: ApplicationFiled: January 9, 2017Publication date: April 27, 2017Inventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Patent number: 9633721Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: GrantFiled: May 19, 2016Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Patent number: 9595322Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: GrantFiled: June 23, 2015Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Publication number: 20160260478Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: ApplicationFiled: May 19, 2016Publication date: September 8, 2016Inventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Patent number: 9384834Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: GrantFiled: March 10, 2015Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Publication number: 20150294720Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: ApplicationFiled: June 23, 2015Publication date: October 15, 2015Inventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Publication number: 20150255155Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.Type: ApplicationFiled: March 10, 2015Publication date: September 10, 2015Inventors: Theodoros A. Antonakopoulos, Evangelos Eleftheriou, Ioannis Koltsidas, Peter Mueller, Aspasia Palli, Roman A. Pletka
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Patent number: 8495281Abstract: A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.Type: GrantFiled: December 4, 2009Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Ilias Iliadis, Theodoros A. Antonakopoulos, Roman Pletka, Xiao-Yu Hu, Roy D. Cideciyan
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Publication number: 20110138103Abstract: A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: IIias IIiadis, Theodoros A. Antonakopoulos, Roman Pletka, Xiao-Yu Hu, Roy D. Cideciyan
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Patent number: 7099257Abstract: Methods are provided for overwriting data in a probe-based data storage device (1) wherein data is represented by the presence and absence of pits formed in a storage surface (4) by a probe of the device. Input data is first coded such that successive bits of a first value in the coded input data are separated by at least one bit of the other value. Overwrite data bits v0, v1, v2, . . . , are generated from the coded input data bits b0, b1, b2, . . . , and the overwrite data bits v0, v1, v2, . . . , are then used to overwrite data on the storage surface (4). According to a first method, the overwrite data bits are generated such that, if a pit represents a bit of said first value in the data storage device (1) then vi={overscore (b)}i?1, for i?1 and v0 has said first value, and if a pit represents a bit of said other value in the data storage device (1) then vi=bi?1 for i?1 and v0 has said other value.Type: GrantFiled: May 19, 2003Date of Patent: August 29, 2006Assignee: International Business Machines CorpInventors: Theodoros Antonakopoulos, Gerd K. Binnig, Evangelos S. Eleftheriou
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Publication number: 20040233817Abstract: Methods are provided for overwriting data in a probe-based data storage device (1) wherein data is represented by the presence and absence of pits formed in a storage surface (4) by a probe of the device. Input data is first coded such that successive bits of a first value in the coded input data are separated by at least one bit of the other value. Overwrite data bits v0, v1, v2, . . . , are generated from the coded input data bits b0, b1, b2, . . . , and the overwrite data bits v0, v1, v2, . . . , are then used to overwrite data on the storage surface (4). According to a first method, the overwrite data bits are generated such that, if a pit represents a bit of said first value in the data storage device (1) then vi={overscore (b)}i−1, for i≧1 and v0 has said first value, and if a pit represents a bit of said other value in the data storage device (1) then vi=bi−1 for i≧1 and v0 has said other value.Type: ApplicationFiled: May 19, 2003Publication date: November 25, 2004Inventors: Theodoros Antonakopoulos, Gerd K. Binnig, Evangelos S. Eleftheriou