Patents by Inventor Theodoros E. Anemikos
Theodoros E. Anemikos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9429619Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.Type: GrantFiled: August 1, 2012Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Theodoros E. Anemikos, Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, Jr.
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Patent number: 9310426Abstract: Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.Type: GrantFiled: September 25, 2012Date of Patent: April 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Theodoros E. Anemikos, Douglas S. Dewey, Pascal A. Nsame, Anthony D. Polson
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Publication number: 20140088947Abstract: Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodoros E. Anemikos, Douglas S. Dewey, Pascal A. Nsame, Anthony D. Polson
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Publication number: 20140039664Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.Type: ApplicationFiled: August 1, 2012Publication date: February 6, 2014Applicant: International Business Machines CorporationInventors: THEODOROS E. ANEMIKOS, Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, JR.
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Publication number: 20130113514Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: International Business Machines CorporationInventors: Theodoros E. Anemikos, Jeanne P. Bickford, Nazmul Habib, Susan K. Lichtensteiger
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Patent number: 8421495Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.Type: GrantFiled: November 3, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Theodoros E. Anemikos, Jeanne P. Bickford, Nazmul Habib, Susan K. Lichtensteiger
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Patent number: 8239811Abstract: Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.Type: GrantFiled: March 24, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Theodoros E. Anemikos, Phillip L. Corson, Mete Erturk, Ezra D. B. Hall, Anthony J. Perri, Sebastian T. Ventrone
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Patent number: 7877714Abstract: A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.Type: GrantFiled: February 27, 2008Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Theodoros E. Anemikos, Jeanne P. Spence Bickford, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson
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Patent number: 7810054Abstract: A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast identically designed integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests operating speeds and power consumption levels of the identically designed integrated circuit devices.Type: GrantFiled: March 4, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Theodoros E. Anemikos, Jeanne Bickford, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson
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Publication number: 20090240452Abstract: Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Inventors: Theodoros E. Anemikos, Phillip L. Corson, Mete Erturk, Ezra D.B. Hall, Anthony J. Perri, Sebastian T. Ventrone
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Publication number: 20090228843Abstract: A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.Type: ApplicationFiled: March 4, 2008Publication date: September 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodoros E. Anemikos, Jeanne Bickford, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson
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Publication number: 20090217221Abstract: A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodoros E. ANEMIKOS, Jeanne P. Spence Bickford, Laura S. Chadwick, Susan K. Lichtensteiger, Anthony D. Polson
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Publication number: 20090115447Abstract: A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodoros E. Anemikos, Michael R. Ouellette, Anthony D. Polson
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Patent number: 7521973Abstract: A method for detecting which of two clock signals is the first to arrive may include providing a sense amplifier comprising first and second nodes located on first and second legs thereof. The sense amplifier is configured such that the first and second nodes have a substantially equivalent initial voltage. The method then includes receiving first and second clock signals. The sense amplifier is configured such that the voltage of the first node increases and the voltage of the second node decreases if the first clock signal arrives before the second clock signal. Similarly, the sense amplifier is configured such that the voltage of the second node increases and the voltage of the first node decreases if the second clock signal arrives before the first clock signal. The method may further include sampling the voltage of at least one of the first and second nodes to determine which of the first and second clock signals was the first to arrive.Type: GrantFiled: June 17, 2008Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Theodoros E Anemikos, Michael Richard Quellette, Anthony D Polson
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Patent number: 7487487Abstract: A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a “schmoo plot” by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.Type: GrantFiled: April 1, 2008Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Anthony D. Polson, David Lackey, Theodoros E. Anemikos, Laura Chadwick