Abstract: An optical driver circuit is described herein having a plurality of drive cells and delay segments between their control signals resulting in the control of the rising and falling edge rates for an optical device driven by the optical driver circuit.

Abstract: Laser circuits are disclosed herein that include, in one example, a proxy laser drive cell and a proxy comparator circuit for deriving a laser driver bias control using one or more constant current supplies. Comparator circuits are disclosed that are adapted to generate an output based on a proxy voltage having first and second voltage components wherein one of the voltage components is developed based on one or more constant current supplies indicative of laser control current.

Abstract: A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.

Abstract: Laser drivers and methods are disclosed including a pulse input for receiving one or more logical pulse control signals, a delay circuit, a main pulse output, and a precharge pulse output for efficiently driving a laser with reduced time delay to desired optical output and reduced power consumption during between optical outputs.

Abstract: An integrated optical transceiver, comprising a laser component, comprising an array of VCSEL diodes formed on a laser diode substrate; a laser driving component, comprising laser diode driving circuitry formed on a laser driving circuitry substrate; a photodiode component, comprising an array of photodiodes formed on a photodiode substrate; and a photodiode driving component, comprising photodiode driving circuitry formed on a photodiode driving circuitry substrate; a first heat sink comprising a connected piece of material to transport excess heat away from the integrated optical transceiver and connected to both the laser and photodiode driving components; and an electrically insulating material separating the photodiode substrate from the first heat sink and being air or dielectric material with a relative dielectric constant ?<10, wherein the electrically insulating material provides a gap having an effective electrical distance of at least 80 ?m between the photodiode substrate and the first heat sin

Abstract: An integrated optical transceiver, comprising a laser component, comprising an array of VCSEL diodes formed on a laser diode substrate; a laser driving component, comprising laser diode driving circuitry formed on a laser driving circuitry substrate; a photodiode component, comprising an array of photodiodes formed on a photodiode substrate; and a photodiode driving component, comprising photodiode driving circuitry formed on a photodiode driving circuitry substrate; a first heat sink comprising a connected piece of material to transport excess heat away from the integrated optical transceiver and connected to both the laser and photodiode driving components; and an electrically insulating material separating the photodiode substrate from the first heat sink and being air or dielectric material with a relative dielectric constant ?<10, wherein the electrically insulating material provides a gap having an effective electrical distance of at least 80 ?m between the photodiode substrate and the first heat si

Abstract: An out-of-band (OOB) signal detector is disclosed. The OOB signal detector may include a first node configured to receive an alternating current (AC) portion and a direct current (DC) portion of an electrical signal. The AC portion may include modulated OOB data carried by the electrical signal. The OOB signal detector may also include a current to voltage processing circuit configured to extract the AC portion of the electrical signal. The OOB signal detector may additionally include a limiting amplifier circuit configured to receive the extracted AC portion and to generate an amplified signal based on the extracted AC portion. The OOB signal detector may further include an analog-to-digital convertor circuit configured to sample the amplified signal and to generate a digital sample that represents the modulated OOB data.

Abstract: An out-of-band (OOB) signal detector is disclosed. The OOB signal detector may include a first node configured to receive an alternating current (AC) portion and a direct current (DC) portion of an electrical signal. The AC portion may include modulated OOB data carried by the electrical signal. The OOB signal detector may also include a current to voltage processing circuit configured to extract the AC portion of the electrical signal. The OOB signal detector may additionally include a limiting amplifier circuit configured to receive the extracted AC portion and to generate an amplified signal based on the extracted AC portion. The OOB signal detector may further include an analog-to-digital convertor circuit configured to sample the amplified signal and to generate a digital sample that represents the modulated OOB data.

Abstract: An out-of-band (OOB) signal detector is disclosed. The OOB signal detector may include a first node configured to receive an alternating current (AC) portion and a direct current (DC) portion of an electrical signal. The AC portion may include modulated OOB data carried by the electrical signal. The OOB signal detector may also include a current to voltage processing circuit configured to extract the AC portion of the electrical signal. The OOB signal detector may additionally include a limiting amplifier circuit configured to receive the extracted AC portion and to generate an amplified signal based on the extracted AC portion. The OOB signal detector may further include an analog-to-digital convertor circuit configured to sample the amplified signal and to generate a digital sample that represents the modulated OOB data.

Abstract: A method to measure and report electromagnetic radiation power includes receiving electromagnetic radiation and generating an electrical signal in response to the received electromagnetic radiation. The electrical signal may have a magnitude based on the power of the electromagnetic radiation. The method also includes applying a logarithmic gain to the electrical signal to generate a logarithmically amplified electrical signal. The method also includes sampling the logarithmically amplified electrical signal to generate a digital sample of the logarithmically amplified electrical signal.

Abstract: An out-of-band (OOB) signal detector is disclosed. The OOB signal detector may include a first node configured to receive an alternating current (AC) portion and a direct current (DC) portion of an electrical signal. The AC portion may include modulated OOB data carried by the electrical signal. The OOB signal detector may also include a current to voltage processing circuit configured to extract the AC portion of the electrical signal. The OOB signal detector may additionally include a limiting amplifier circuit configured to receive the extracted AC portion and to generate an amplified signal based on the extracted AC portion. The OOB signal detector may further include an analog-to-digital convertor circuit configured to sample the amplified signal and to generate a digital sample that represents the modulated OOB data.

Abstract: A method to measure and report electromagnetic radiation power includes receiving electromagnetic radiation and generating an electrical signal in response to the received electromagnetic radiation. The electrical signal may have a magnitude based on the power of the electromagnetic radiation. The method also includes applying a logarithmic gain to the electrical signal to generate a logarithmically amplified electrical signal. The method also includes sampling the logarithmically amplified electrical signal to generate a digital sample of the logarithmically amplified electrical signal.

Abstract: An example bandpass filter calibration system includes a MUX, first and second signal sources coupled to inputs of the MUX, a bandpass filter coupled to an output of the MUX, a rectification circuit including a plurality of rectifiers having a corresponding plurality of rectifier outputs coupled to an output of the bandpass filter, a summer having a plurality of inputs coupled to the plurality of rectifier outputs, a low pass filter coupled to an output of the summer, an ADC coupled to an output of the low pass filter, and a calibration processor unit coupled to an output of the ADC. The calibration processor unit controls the MUX to selectively apply the first signal source and the second signal source to the bandpass filter and calibrates the bandpass filter by a least one of increasing filter center frequency and decreasing filter center frequency of the bandpass filter.

Abstract: An example bandpass filter calibration system includes a MUX, first and second signal sources coupled to inputs of the MUX, a bandpass filter coupled to an output of the MUX, a rectification circuit including a plurality of rectifiers having a corresponding plurality of rectifier outputs coupled to an output of the bandpass filter, a summer having a plurality of inputs coupled to the plurality of rectifier outputs, a low pass filter coupled to an output of the summer, an ADC coupled to an output of the low pass filter, and a calibration processor unit coupled to an output of the ADC. The calibration processor unit controls the MUX to selectively apply the first signal source and the second signal source to the bandpass filter and calibrates the bandpass filter by a least one of increasing filter center frequency and decreasing filter center frequency of the bandpass filter.

Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2? radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2&pgr; radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Abstract: Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Abstract: A power controller regulates power from a power source coupled to a power source input to a load coupled to a load output, and this power controller includes a switch and a switching controller. The switch is coupled between the power source input and the load output wherein the switch is switched on and off responsive to an input signal. The switching controller is coupled to the switch wherein the switching controller generates the input signal so that the switch is switched on and off to provide a regulated power output to the load output during active load operations and so that the switch couples the power source to the load output without switching to provide an unregulated power output during stand-by load operations. Related methods and radiotelephones are also discussed.