Abstract: The electronic bit generator includes a clock, a pseudo-random sequence generator, a counter having the same capacity as the pseudo-random sequence generator and a comparator. One input of the comparator is connected from the output of the pseudo-random sequence generator, and the other input is connected from the data output of the counter. The output of the comparator is connected to the reset input of the counter and to the clock input of the pseudo-random sequence generator. The clock input of the counter is connected from the output of the clock and the comparator output constitutes the output of the electronic bit generator. The comparator comprises a plurality of stages having a number which is equal to the length of the output binary word of the pseudo-random sequence generator. Each comparator stage includes an exclusive-OR gate, the two inputs of which are respectively connected from the outputs of the stages having the same rank in the pseudo-random sequence generator and in the counter.