Abstract: A method and apparatus for reducing convergence time in a digital filter. When the digital filter is initially run, the coefficients in the digital filter are adjusted to reduce error in the output of the digital filter. When the adjusted coefficients meet a selected error level, these coefficients are stored in a memory and the digital filter filters data. The next time the digital filter is run, the stored coefficients are loaded into the digital filter and a number of iterations are run in which the coefficients are adjusted. Then, a determination is made as to whether the error level meets a threshold that may be the same as the selected error level. If the coefficients meet the threshold, the coefficients are stored in the memory and the filter is then used to filter data.

Abstract: A method and apparatus for reducing convergence time in a digital filter. When the digital filter is initially run, the coefficients in the digital filter are adjusted to reduce error in the output of the digital filter. When the adjusted coefficients meet a selected error level, these coefficients are stored in a memory and the digital filter filters data. The next time the digital filter is run, the stored coefficients are loaded into the digital filter and a number of iterations are run in which the coefficients are adjusted. Then, a determination is made as to whether the error level meets a threshold that may be the same as the selected error level. If the coefficients meet the threshold, the coefficients are stored in the memory and the filter is then used to filter data.

Abstract: The high speed multiplier takes advantage of results from previous calculations by recognizing that in many cases the multiplicand between a first and second multiplication differs only slightly. Thus, the present system divides the multiplicand into a cache lookup bit (CLB) and a table lookup bit (TLB). The results of a first multiplication are stored in a cache. The CLB of a of the multiplicand in the second multiplication is then compared to the CLB of the multiplicand in the second multiplication. If the CLB matches, the product of the first multiplication is retrieved. The product of the TLB of the multiplicand and the multiplier is then retrieved from a lookup table and either added or subtracted from the retrieved product.

Abstract: A non-volatile storage device storing a data bit received from a bitline via an accessing circuit. A coupling circuit couples either the bitline, or a complementary bitline to a biasing circuit dependent on the logic level of the data bit stored in the storage device. The biasing circuit generates a match signal when a data bit having the same logic level as the stored data bit is applied to the bitline.