Abstract: Example methods and systems for calibrating one or more light sources are described. One example method includes determining a position of at least three photosensors relative to a world frame, controlling an orientation of at least one light source so as to cause the at least one light source to project a light beam across an area encompassing the at least three photosensors, receiving signals indicating a sensing of a light beam directed at one of the photosensors, determining orientations of the at least one light source that cause a signal at one of the photosensors, and based on the position of the at least three photosensors and the orientations of the at least one light source that cause a signal at one of the photosensors, determining a transformation from a local frame of the at least one light source to the world frame.

Abstract: A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

Abstract: A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.