Abstract: A lead-frame for connecting and supporting an integrated circuit having an apertured frame with dimensions smaller than the corresponding dimensions of the chip so that chip-pad shoulder can be eliminated and the chip attach fillet is made remote from the chip corner.

Abstract: A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

Abstract: The present invention is directed to a method for the lamination of fluoropolymers to the surfaces of metals, and especially to copper, gold, and platinum, and to printed circuit board (PCB) substrate at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of metals in the presence of a functional monomer and an adhesive such as an epoxy resin. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The laminated fluoropolymer-metal or fluoropolymer-PCB substrate interfaces exhibit T-peel strengths of no less than 8 N/cm. This invention can also be applied to substantially improve the adhesion between PCB substrates and metals.

Abstract: The present invention is directed to a method for the lamination of metals, and especially copper, to the surface of polyimides and derivatives of polyimides at temperatures substantially below the curing temperature of the imide polymers. More specifically, the invention is directed to a method for surface modification of polyimides and derivatives of polyimides by thermal graft copolymerization and interfacial polymerization with concurrent lamination of the metal of interest in the presence of an appropriate functional monomer. The process can be carried out under atmospheric conditions and either in the presence or the complete absence of an added polymerization initiator. The so laminated polyimide-metal interfaces exhibit T-peel adhesion strengths in excess of 16 N/cm. The adhesion strength also exceeds the fracture strength of polyimide films with a thickness of 75 &mgr;m.

Abstract: The present invention relates to the structure and process of forming metal surfaces on the bare metal interconnect of a semiconductor chip. The metal chip comprises metal interconnect formed on a semiconductor substrate and at least a portion of the metal interconnect is exposed to the environment. In one aspect of the invention, the process comprises applying a noble metal on the exposed portion of the metal interconnect and performing a chemical process that causes a layer of the noble metal to convert into a bondable layer compatible with a conventional wire bonding. The process also comprises bonding a metal wire to the bondable layer.

Abstract: A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

Abstract: The present invention is directed to a method for the lamination of metals, and especially copper, to the surfaces of fluoropolymers at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of a metal (e.g. copper) in the presence of a functional monomer. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The so-laminated fluoropolymer-metal interfaces exhibit T-peel strengths of no less than 8 N/cm and delaminate via cohesive failure inside the fluoropolymer.

Abstract: The invention is directed to a chip-sized package (CSP) and method for making a CSP which is simple to manufacture, less costly and more compact, thus being truly a chip-sized package. The inventive CSP has a chip that has an array of chip ports on an active surface, such as an array of solder or metal bumps or any other conductive material. The chip may be held in a cavity of a frame by a pair of frame tie-bars. An encapsulant encapsulates the chip and portions of the chip ports located near the active surface, leaving portions of the chip ports located away from the active surface exposed. Package ports, such as solder balls may be attached to the portions of the chip ports located away from the active surface and used to attach the CSP to a printed circuit board. Various methods are used to leave portions of the chip ports located away from the active surface exposed from the encapsulant. The encapsulant may be removed by laser or grinding to expose portions of the chip ports.

Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.

Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.

Abstract: The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.