Abstract: An embodiment of the present invention is a technique to provide a secure authentication of chipset configuration. A first chipset configuration (CC) register set in an input/output (I/O) manageability engine (ME) partition authenticates and controls enabling a CC functionality. The I/O ME partition manages I/O resources shared with a processor in a secure manner. A second CC register set in a processor interface space provides the CC functionality. The second CC register set includes a global enable register having an enable field securely accessible to the I/O ME partition in a read and write-once accessibility and accessible to the processor via the processor interface space in a read-only accessibility.

Abstract: Various embodiments adjust the rate at which periodic flow control updates are transmitted when in a lower power or power saving state. One embodiment transmits flow control updates across a bus based upon a first rate in response to a normal power mode and transmits second flow control updates across the bus based upon a second rate in response to a power saving mode.

Abstract: Method and apparatus for programmable completion tracking logic to support multiple virtual channels. In one embodiment, the apparatus includes a controller having the programmable completion tracking logic for supporting multiple virtual channels. In one embodiment, a completion tracking queue is programmable to provide a predetermined number of entries to store upstream non-posted (NP) read request information corresponding to a virtual channel from a plurality of virtual channels supported by the controller. In one embodiment, the predetermined number of entries are shared among the plurality of virtual channels according to a minimum entry value and a maximum entry value defined for each respective virtual channel. Other embodiments are described and claimed.