Abstract: In the field of programmable devices, such as FPGAs, comprising multi-gigabit transceiver units, it is desirable to communicate a data stream of a first data rate between the programmable devices at a second data rate. In order to achieve this aim, the data stream is read from a first buffer at the second data rate by a first device and communicated to a second device at the second data rate. When the buffer empties, idle bits are inserted in the absence of data. Upon receipt by the second device, the idle bits are identified and removed prior to buffering.