Abstract: The present disclosure relates to a catalyst for ammonia decomposition, a manufacturing method therefor, and a method for producing hydrogen using the same. More particularly, the present disclosure relates to a catalyst for ammonia decomposition, a manufacturing method therefor, and a method for producing hydrogen using the same, in which by manufacturing a catalyst for decomposition of ammonia using a solvothermal synthesis method to which alcohol is applied, an ammonia conversion rate can be improved due to excellent catalytic activity in an ammonia decomposition reaction, and hydrogen can be efficiently produced from ammonia due to long-term stability even at a high temperature and for long periods of time.

Abstract: The present invention relates to an ammonia decomposition catalyst that converts ammonia into hydrogen and nitrogen. The catalyst includes ruthenium (Ru) as an active catalytic component and a composite oxide solid solution (LaxCe1-xOy) including lanthanum oxide and cerium oxide as a catalyst support. The present invention also relates to an ammonia decomposition method using the catalyst and a hydrogen production method using the catalyst.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

Abstract: Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.

Abstract: Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.

Abstract: An integrated circuit with voltage regulator circuitry is provided. The voltage regulator circuitry may include an adaptive bleeder circuit. The adaptive bleeder circuit may include one or more switchable current leaker paths and an associated bleeder control circuit having current sensing circuitry and voltage comparison circuitry. The current sensing circuitry may monitor the amount of current that is being delivered to a load circuit, whereas the voltage comparison circuitry may output control signals that selectively activate one or more of the current leaker paths depending on the monitored current values. Adaptive bleeder circuit configured in this way can help maintain stability of the voltage regulator while minimizing dynamic power consumption.

Abstract: A startup circuit to ensure a bandgap reference circuit reliably starts up or recovers from a noise disturbance is provided. The startup circuit incorporates a pull down resistor to detect the bandgap reference circuit being in a disabled state. The startup circuit creates a positive feedback loop to force the bandgap reference circuit out of a disabled state. Consequently, whenever the power supply for the bandgap reference circuit sags or if bandgap output collapses, the output of the bandgap circuit reliably ramps back up to the expected level.

Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry may contain a drive transistor that is controlled by the output of an operational amplifier. The drive transistor may supply a regulated voltage to a load. The operational amplifier may compare a reference voltage and a feedback signal at its inputs. The operational amplifier may include first and second stages. An adjustable resistor may be provided between the first and second stages. Control circuitry may control the resistance of the adjustable resistor based on the amount of current flowing through the load to ensure stable operation of the voltage regulator circuitry. Overshoot and undershoot detection and compensation circuitry may compensate for overshoot and undershoot in the regulated voltage. Voltage ramp control circuitry may be used to control the ramp rate of the regulated voltage.

Abstract: A low dropout (LDO) voltage regulator with unconditional frequency compensation is presented. The low dropout voltage regulator is implemented using a two-stage operational amplifier. The first stage amplifier has two input transistors, each of which is connected to a diode-connected transistor. A transistor is connected in parallel to the diode-connected transistors to increase the gain of the first stage amplifier. The LDO voltage regulator has a compensation capacitance input between the first stage amplifier and the second stage amplifier and a voltage on the compensation capacitance input adjusts the current through the diode-connected transistors, as well as the gain of the first stage amplifier. The second stage amplifier receives output from the first stage amplifier, and a compensation capacitor is connected between the compensation capacitance input of the operational amplifier and the output node of the LDO voltage regulator.

Abstract: A charge pump circuit is provided that has a controllable ramp rate. The charge pump circuit may receive a control signal from a control circuit. The control signal may be asserted by the control circuit to turn on the charge pump circuit. When the charge pump circuit is turned on, the charge pump circuit produces an output voltage. The output voltage ramps up from an initial value to a desired target value. During the ramp up process, a ramp rate regulation circuit monitors the output voltage and ensures that the ramp rate does not exceed a desired maximum value. A capacitor may be charged at a desired ramp rate to use as a time-varying reference voltage. A feedback circuit may be used to maintain the output voltage at the desired target value once the ramp-up process is complete.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: Power regulator circuitry is provided for powering loads such as programmable memory element arrays on integrated circuits. The power regulator circuitry may have control circuitry that generates a first digital control signal to turn on and off a regulated power supply circuit and a second digital control signal to turn on and off a switch-based power supply circuit. The outputs of the regulated power supply circuit and switch-based power supply circuit may be connected to an output terminal for the power regulator circuitry. The first and second digital control signals may be used to ensure that the regulated power supply circuit is turned on before the switch-based power supply circuit is turned off. The switch-based power supply circuitry may contain serially connected transistors. The transistors may be turned off in an order that prevents latchup.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry may contain a drive transistor that is controlled by the output of an operational amplifier. The drive transistor may supply a regulated voltage to a load. The operational amplifier may compare a reference voltage and a feedback signal at its inputs. The operational amplifier may include first and second stages. An adjustable resistor may be provided between the first and second stages. Control circuitry may control the resistance of the adjustable resistor based on the amount of current flowing through the load to ensure stable operation of the voltage regulator circuitry. Overshoot and undershoot detection and compensation circuitry may compensate for overshoot and undershoot in the regulated voltage. Voltage ramp control circuitry may be used to control the ramp rate of the regulated voltage.

Abstract: Voltage regulator circuitry is provided. The voltage regulator circuitry may contain a drive transistor that is controlled by the output of an operational amplifier. The drive transistor may supply a regulated voltage to a load. The operational amplifier may compare a reference voltage and a feedback signal at its inputs. The operational amplifier may include first and second stages. An adjustable resistor may be provided between the first and second stages. Control circuitry may control the resistance of the adjustable resistor based on the amount of current flowing through the load to ensure stable operation of the voltage regulator circuitry. Overshoot and undershoot detection and compensation circuitry may compensate for overshoot and undershoot in the regulated voltage. Voltage ramp control circuitry may be used to control the ramp rate of the regulated voltage.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: A charge pump circuit is described. The charge pump circuit includes: a first pumping stage including a first switch and a second switch coupled to the first switch; and at least a second pumping stage coupled to the first pumping stage, where the second pumping stage includes a third switch and a fourth switch coupled to the third switch; where the first and second switches are in opposite states, further where immediately prior to the first switch transitioning from an off state to an on state, the second switch and the fourth switch are on. In one embodiment, the third and fourth switches are in opposite states, where immediately prior to the third switch transitioning from an off state to an on state, the second switch and the fourth switch are on.