Abstract: In one embodiment, the present invention includes an integrated circuit comprising a radio frequency communication channel having a mixer and a programmable analog filter coupled to an output terminal of the mixer. The integrated circuit further comprises a digital-to-analog converter providing an AC signal to the digitally programmable analog filter, an analog-to-digital converter (ADC) coupled to an output terminal of the digitally programmable analog filter, and a digital calibration circuit that adjusts the filter frequency according to measurements calculated from the data from the ADC. During a first calibration phase, the filter frequency is adjusted to a first frequency and a first signal is measured. During a second calibration phase, the filter frequency is adjusted to a second frequency approximately equal to a frequency of the AC signal, and a second signal is measured. The filter frequency is further adjusted based on measured values of the first and second signals.

Abstract: A high voltage operational amplifier receives a low voltage differential input signal at a low voltage transconductance stage (3) which provides a differential current output. An intermediate stage (5) has a differential current input coupled to the differential current output of the transconductance stage (3) via a voltage buffer stage (4) and produces a voltage output at a high voltage level but with low voltage swings providing a voltage representing the differential input signal. An interface stage (9) is coupled to receive the voltage output of the intermediate stage (5) and provides voltage and current outputs representing the voltage output of the intermediate stage (5). Output sourcing and sinking stages (6 and 7) receive the voltage and current outputs of the interface stage (9), respectively, and produce high currents representative of the differential input signal.

Abstract: A current sourcing output stage for a high voltage operational amplifier receives a low voltage input signal (V.sub.IN) and provides a high current output signal corresponding to the low voltage input signal at an output terminal (8). A first PNP transistor (Q1) is coupled between a voltage supply (V.sub.CC) and a plurality of cascaded PNP transistors (Q2, Q3, Q8-Q11) coupled to the output terminal (8). The base of the first PNP transistor (Q1) is coupled to receive the input signal (V.sub.IN) and the bases of the cascaded PNP transistors are coupled to receive different bias voltages A control circuit (Q5-Q7, R1-R5) is coupled to the voltage supply (V.sub.