Abstract: According to one embodiment of the invention, a wireless network device comprises wireless logic and a heat dissipation unit that encases the wireless logic. The heat dissipation unit includes an antenna dome array that comprises a top surface having a convex-shaped outer periphery with a plurality of antenna elements positioned along the outer periphery.

Abstract: According to one embodiment of the invention, a wireless network device comprises wireless logic and a heat dissipation unit that encases the wireless logic. The heat dissipation unit includes an antenna dome array that comprises a top surface having a convex-shaped outer periphery with a plurality of antenna elements positioned along the outer periphery.

Abstract: According to one embodiment of the invention, an apparatus comprises an input port, a measuring circuit and a processor. The measuring circuit is adapted to measure a power parameter associated with power supplied over a communication media to the input port. The processor includes a plurality of logic units. Each logic unit is configured to be activated in series to control power usage of the apparatus.

Abstract: According to one embodiment of the invention, an apparatus comprises an input port, a measuring circuit and a processor. The measuring circuit is adapted to measure a power parameter associated with power supplied over a communication media to the input port. The processor includes a plurality of logic units. Each logic unit is configured to be activated in series to control power usage of the apparatus.

Abstract: A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.

Abstract: A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.

Abstract: Etch residue, resulting from a process used in forming a via, is removed using a process that does not require using a liquid chemical solvent and does not result in excessive charge build-up in the via. One step is to use a fluorocarbon and oxygen. These gases are energized by both microwave and RF. Another step is to introduce argon, in addition to the other two gases, also energized by microwave and RF. This has the effect of removing any additional residue which tends to stick on the surface above the via as well completing the removal of etch residue in the via. An additional step is simply to apply de-ionized water to remove any remaining fluorinated residue that, as a result of the preceding two steps, is highly soluable in water.

Abstract: A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of electrodes from an RF power source. A first gas flow is circulated through the reaction chamber during the application of power. This first gas flow includes a first argon flow, a first oxygen flow, and a first fluorocarbon flow. Applying the first quantity of low frequency power creates a first plasma for etching a portion of a nitride layer arranged above the semiconductor substrate.

Abstract: Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl3, Cl2, N2 and CF4 to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.

Abstract: A method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.

Abstract: The present invention is directed to a method of fabricating very thin silicon nitride spacers on a transistor, and to a device comprising such spacers. In one illustrative embodiment, the method comprises forming a gate dielectric above a surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and forming a layer of silicon nitride above the substrate. The method further comprises performing at least one anisotropic etching process on the layer of silicon nitride using an etching recipe comprised of helium (He), sulfur hexafluoride (SF6) and hydrogen bromide (HBr). The transistor of the present invention is comprised of a gate dielectric positioned above the surface of a semiconducting substrate and a gate conductor positioned above the gate dielectric.

Abstract: An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a "large tilt angle" (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor.

Abstract: The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a first layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said first layer of dielectric material and between said source/drain regions, and forming a second layer of dielectric material above said first layer of dielectric material. The method further comprises forming a layer of polysilicon above the second layer of dielectric material, forming a gate dielectric above said layer of polysilicon, and forming a gate conductor above said gate dielectric.

Abstract: An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in the substrate and a first insulating layer in the trench that has a bottom, a first sidewall and a second sidewall. Silicon nitride is deposited in the trench. Silicon nitride is removed from the bottom of the first insulating layer to establish a layer of silicon nitride on the first and second sidewalls by performing a first plasma etch of the deposited silicon nitride with an ambient containing He, SF.sub.6, and HBr, and a second plasma etch with an ambient containing He, SF.sub.6, and HBr. An insulating material is deposited in the trench. The method provides for reliable manufacture of nitride liners for trench isolation structures. Scaling is enhanced and the potential for parasitic leakage current due to liner oxide fracture or irregularity is reduced.

Abstract: A dry etch process is presented wherein a semiconductor substrate is introduced into a reaction chamber between a first electrode and a second electrode. The semiconductor substrate may be positioned on the first electrode. A main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow at a fluorocarbon flow rate is established into the reaction chamber. RF power at a low frequency may then be applied to the first electrode for creating a fluorine-deficient plasma. An oxide layer arranged above the semiconductor substrate is exposed to the fluorine-deficient plasma for etching, in a single step, a portion of the oxide layer.

Abstract: A method is provided for fabricating a transistor, the method including forming a semiconducting layer above a substrate layer, forming a first dielectric layer above the semiconducting layer and forming a sacrificial layer above the first dielectric layer. The method also includes forming an opening in the sacrificial layer, the first dielectric layer and the semiconducting layer to expose a channel region in the substrate layer. The method further includes forming a gate dielectric above the channel region in the substrate layer within the opening and forming a gate conductor above the gate dielectric within the opening. Moreover, the method includes removing the sacrificial layer to expose sides of the gate conductor and introducing a dopant into the semiconducting layer to form doped source/drain regions. In addition, the method includes forming dielectric spacers adjacent the gate conductor.

Abstract: ST-cut and AT-cut quartz seed bodies (18,40) for quartz crystal synthesis and method (100) for making the same are disclosed. An extended quartz seed body (18) having an angle of about 42.75.degree. rotated about a X axis (20) from a +Z axis (22) to a -Y axis (24) and defining a ST-cut is provided and a quartz crystal bar (32) is grown thereupon. Analogously, an extended quartz seed body (40) having an angle of about 35.25.degree. rotated about a X axis (20) from a +Z axis (22) to a -Y axis (24) and defining an AT-cut is provided and a quartz crystal bar (48) is grown thereupon. In each case, the subsequent quartz crystal bar (32,48) may be wafered parallel to the seed body (18,40) thereby; reducing waste (68), recovering the seed body (18,40) for reuse, producing wafers (70) without intervening seed portions, and increasing factory capacity.

Abstract: An etchant gas and process for using the etchant gas is provided for removing a spin-on glass (SOG) material. The gas composition is chosen as a combination of CHF.sub.3, O.sub.2 and Ar inserted into a parallel electrode reactor. The reactor pressure is maintained between 755 to 845 mTorr while the rf power is maintained at approximately 400 watts. CHF.sub.3 flow rate is optimally chosen between 55 and 65 sccm, with O.sub.2 flow rate approximately equal to 15 sccm and Ar flow rate approximately equal to 266 sccm. The processing parameters are optimally chosen to remove SOG at a rate exceeding 1.5 times the rate in which underlying TEOS-based oxide is removed. Accordingly, the present gas composition and processing methodology ensures SOG is completely removed in thicker areas overlying sparsely spaced interconnect, and that underlying oxide is not removed beneath thinner SOG residing above densely spaced interconnect.

Abstract: ST-cut and AT-cut quartz seed bodies (18,40) for quartz crystal synthesis and method for making the same are disclosed. An extended quartz seed body (18) having an angle of about 42.75.degree. rotated about a X axis (20) from a +Z axis (22) to a -Y axis (24) and defining a ST-cut is provided and a quartz crystal bar (32) is grown thereupon. Analogously, an extended quartz seed body (40) having an angle of about 35.25.degree. rotated about a X axis (20) from a +Z axis (22) to a -Y axis (24) and defining an AT-cut is provided and a quartz crystal bar (48) is grown thereupon. In each case, the subsequent quartz crystal bar (32,48) may be wafered parallel to the seed body (18,40) thereby; reducing waste (68), recovering the seed body (18,40) for reuse, producing wafers (70) without intervening seed portions, and increasing factory capacity.