Patents by Inventor Thien Tung Nguyen

Thien Tung Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6322660
    Abstract: A chromator for monitoring the end point of a plasma etching process is placed remotely from the window of a plasma etching chamber and is optically coupled to the window with a fiber optic cable bundle. The fiber optic cable bundle includes a first and a second bracket. Each bracket is specially designed to be compatible with existing chromator and plasma etching chambers. The first bracket, which attaches to the chamber, includes a plurality of slots for allowing the bracket to be axially and vertically adjusted to find the optimal optical point. Accordingly, the likelihood of the chromator properly detecting the end point is maximized. An inventive method a includes optically coupling the remotely located chromator by connecting a fiber optic cable bundle having a first bracket to the chamber, axially adjusting the bracket to find the optimal location for detecting the end point, and securing the first bracket to the chamber. The second bracket of the fiber optic cable bundle is connected to a chromator.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: November 27, 2001
    Assignee: Advanced Micro Devices
    Inventors: Michael Patrick McFee, Stephanie Annette Grahn, Thien Tung Nguyen
  • Patent number: 6180465
    Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A dielectric layer is then formed on the surface of the substrate, portions of which are then etched to define a channel opening for the device. A uniform nitride layer is formed over the surface of the substrate. The nitride layer is then etched to create nitride sidewall spacers. Additionally, the channel region is then etched to remove the doped portions of the active region. A gate dielectric is then formed, the gate dielectric including a nitrogen bearing oxide and a high K material. A gate conductor is then formed upon the high K material. A silicidation step is then performed. In alternative embodiments, the source/drain region is not formed and the source and drain are doped after the gate is complete. In the embodiment, the gate resides upon the active region and etching into the active region is not required.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: January 30, 2001
    Assignee: Advanced Micro Devices
    Inventors: Mark I. Gardner, Thien Tung Nguyen