Abstract: The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Abstract: The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Abstract: An integrated module contains a microcontroller and a code/data memory, it being possible for an access to the memory and an external data transfer terminal to be controlled by the microcontroller during normal operation. Furthermore, the carrying out of a test sequence for the functional testing of the memory can be controlled by the microcontroller in a test operation. In a method for checking the functionality of the memory, a command sequence on the basis of which the microcontroller controls the carrying out of the test sequence is read into the module externally before the beginning of the test operation. The command sequence is executed on the microcontroller and defect data are stored in a defect data memory under the control of the microcontroller. Therefore, it is possible to carry out a self-test of the memory, but no additional BIST hardware has to be provided for this purpose.