Abstract: A matrix photosensitive detector organized in pixels and to a method for producing the detector, the detector comprising: a flat substrate having multiple interconnect levels connected to one another by through vias, a photodetector grouping together the pixels of the photosensitive detector, arranged on a first external face of the flat substrate and configured to bring about conversion of radiation to which the detector is sensitive into an electrical signal by each of the pixels, semiconductor microcircuits configured to drive and read out each of the pixels, the microcircuits being arranged facing each of the pixels or between adjacent pixels perpendicular to the substrate, each microcircuit being carried on a microsubstrate independent from the flat substrate of the photosensitive detector, the microcircuits being connected individually to the flat substrate at one of its interconnect levels.

Abstract: A digital detector includes a conversion block intended to convert incident radiation into electric charge; an electronic card that converts the electric charge into a digital image, the conversion block comprising N conversion stages superposed on one another, N being an integer between 2 and M, each of the N conversion stages comprising: a monolithic substrate; a first converter assembly in the form of a polygonal matrix array, M being the number of sides of the polygonal matrix array, M preferably being equal to 4, and configured so as to generate the electric charge on the basis of the incident radiation; an addressing and driving module for addressing and driving the matrix array, the addressing and driving module being arranged on the monolithic substrate along one side of the polygonal matrix array; each of the N conversion stages being oriented by at least 1/M of a turn with respect to the other N?1 conversion stages of the conversion block, and with an orientation distinct from the other N?1 conversi

Abstract: A digital detector includes a conversion block intended to convert incident radiation into electric charge; an electronic card that converts the electric charge into a digital image, the conversion block comprising N conversion stages superposed on one another, N being an integer between 2 and M, each of the N conversion stages comprising: a monolithic substrate; a first converter assembly in the form of a polygonal matrix array, M being the number of sides of the polygonal matrix array, M preferably being equal to 4, and configured so as to generate the electric charge on the basis of the incident radiation; an addressing and driving module for addressing and driving the matrix array, the addressing and driving module being arranged on the monolithic substrate along one side of the polygonal matrix array; each of the N conversion stages being oriented by at least 1/M of a turn with respect to the other N?1 conversion stages of the conversion block, and with an orientation distinct from the other N?1 conversi

Abstract: The present invention relates to a photosensitive device comprising a matrix of photosensitive pixels, in particular of the type produced by techniques for depositing semiconductor materials. The invention relates more particularly (but not exclusively) to the driving of such devices used for detecting radiological images. It also relates to a method of driving the photosensitive device. The photosensitive device includes means for adjusting the amplitude of the bias, allowing separate adjustment of the amplitude of the bias of the photosensitive pixels (P1 to P9; P401 to P409). The method of driving the photosensitive device consists, in the calibration phase, in adjusting the amplitude of the bias of each of the photodetector elements (Dp) separately from one another, so as to bring the output saturation levels of the two photosensitive pixels into maximum coincidence.

Abstract: A process for controlling a photosensitive device including at least one photosensitive point with a photodiode connected to a switching element. The process submits the photosensitive point to successive imaging cycles. Between a first imaging cycle and a second imaging cycle, the process produces a holding phase terminating at the start of the second imaging cycle. During this holding phase, whose duration is equal to several equal time intervals that are as short as possible, the photosensitive point is exposed to an optical flash at the start of each time interval. Between successive optical flashes, the photodiode is reverse biased. The junction region between the photodiode and the switching element has substantially the same potential at the end of each time interval.

Abstract: A process for correcting noise level of an image detector including photosensitive points arranged in rows and in columns. Within each row, the points are distributed into detector points and into corrector points. The detector points deliver a measurement value dependent on a luminous cue to which they are exposed. The corrector points deliver a dark value serving in the correction of the measurement values. Within at least one row, the detector points are distributed into at least two groups and the measurement values are corrected with a first or a second correction value depending on the group from which they originate. Such a process may find application to digitized-image detectors.

Abstract: A method for temperature compensation of sensitivity of an image including photosensitive spots each with a photodiode connected to read circuits. The photosensitive spots are divided into detecting photosensitive spots, detecting an image when exposed to information carrying the image and sensitive to this information, and into blind spots protected from the information. When the photosensitive spots are taken to a reference temperature, an average leakage current in the photodiodes of the blind photosensitive spots is calculated and a first average is generated from signals from the blind photosensitive spots during a read operation. When the photosensitive spots are taken to an ambient temperature to be determined, another average is generated from signals from the blind photosensitive spots during another read operation. The ambient temperature is calculated from the average leakage current and from the distance between the two averages.

Abstract: The present invention relates to a photosensitive device comprising a matrix of photosensitive pixels, in particular of the type produced by techniques for depositing semiconductor materials. The invention relates more particularly (but not exclusively) to the driving of such devices used for detecting radiological images. It also relates to a method of driving the photosensitive device.

Abstract: A method and device for temperature compensation of an image detector including photosensitive spots sensitive to ambient temperature, each connected to a row conductor and a column conductor. The photosensitive spots are connected by their conductors to a read circuit. The photosensitive spots are divided into detecting photosensitive spots to be exposed to light information corresponding to the image to be detected, the read circuits associated with these photosensitive spots each delivering a measurement voltage representative of the image to be detected, and into blind photosensitive spots protected from the light information, the read circuits associated with these blind photosensitive spots each delivering a dark voltage serving for temperature compensation.

Abstract: A drive process for an array of photosensitive points produced on a semiconductor material. Each of the points has a photodiode connected in series with a switch element. The photodiode is reverse-biased and produces charges when it is exposed to a light signal during an imaging phase. Before the imaging phase, the photosensitive points are illuminated with an additional light flux whose intensity causes the photodiode to conduct in the forward direction and then in applying a biasing pulse to the photosensitive points in order to return the photodiode to reverse bias. Thus, a current is produced which has the effect of reducing a remanence effect in the semiconductor material.

Abstract: A circuit for reading charges injected at an input of the circuit including a read MOS transistor having first and second electrodes corresponding to a drain-source pair and for reading charges having a first polarity that are injected at the input of the circuit. The read MOS transistor is controlled by a control voltage that varies in a manner substantially inversely proportional to an input voltage of the circuit.

Abstract: This is a method for temperature compensation of the sensitivity of an image comprising photosensitive spots (O1 to O6, R1 to R9) each with a photodiode (Dp), these being connected to read circuits (30a, 30b). The photosensitive spots are divided into detecting photosensitive spots (R1 to R9), capable of detecting an image when they are exposed to information carrying the image and are sensitive to this information, and into blind spots (O1 to O6) protected from the information.

Abstract: This is a method for temperature compensation of an image detector comprising photosensitive spots (O1 to O6, R1 to R9), these being sensitive to ambient temperature, each connected to a row conductor (Y1 to Y3) and a column conductor (W1, W2, Z1 to Z3). Each of the photosensitive spots is connected via one of its conductors to a read circuit (30a, 30b). The photosensitive spots are divided into detecting photosensitive spots (R1 to R9), intended to be exposed to light information corresponding to the image to be detected, the read circuits (30b) associated with these photosensitive spots each delivering a measurement voltage representative of the image to be detected, and into blind photosensitive spots (O1 to O6) protected from the light information, the read circuits (30a) associated with these blind photosensitive spots each delivering a dark voltage serving for temperature compensation.

Abstract: A photosensitive device comprises: photosensitive cells located at the intersection of at least one addressing conductor and one read conductor, a cell comprising a photosensitive diode connected to a read conductor and to at least one diode having a switching function connected to an addressing conductor, these diodes having a common point; addressing means connected to at least one addressing conductor; charge-reading means connected to at least one read conductor.

Abstract: An integrator circuit for photogenerated charges which limits linearity defects. The circuit includes an integration capacitor with a first blade connected to a reference potential and a second blade having a variable potential which receives photogenerated charges. The circuit also includes a resetting MOS transistor of a first type connected to the variable potential at one terminal and to a supply potential on another. The MOS transistor represents a straight capacitance in parallel with the integration capacitor. One or more MOS transistors of a second type are connected to the variable potential and each have a stray capacitance in parallel with the integration capacitor. A variation in the voltage across the terminals of the integration capacitor causes a variation in the value of the straight capacitances of the MOS transistors of the second type which tends to compensate for the variation in the stray capacitance of the MOS transistor of the first type.

Abstract: A circuit for the reading of charges injected at its input comprises a read MOS transistor, the type of which conditions the polarity of the charges that the read circuit is capable of reading without getting blocked, and an integration capacitor mounted between a first electrode of the drain-source pair of the read MOS transistor and a reference potential. The input of the circuit is at the second electrode of the drain-source pair of the read MOS transistor. The injected charges must cross the read MOS transistor to be integrated by the capacitor. The read MOS transistor is controlled by a control voltage that varies in a manner that is substantially inversely proportional to the input voltage.

Abstract: A device for copying a voltage (Ve) comprises a pair of series-connected MOS transistors, their sources forming a common point. The voltage (Ve) to be copied is applied between the gate of the first MOS transistor of the pair and a reference. Means are provided to inject a flux of electrons at a common point. A storage capacitor has a first terminal connected to the drain of the second MOS transistor and a second terminal designed to be biased. Means dictate a potential at the drain of the second MOS transistor and then let it vary so that the flux of electrons is stored in the storage capacitor while at the same time decreasing in the second MOS transistor to the benefit of the first one. The copied voltage Vs is available, after stabilization, between the first terminal of the storage capacitor and the reference. Application in particular to circuits for the reading of charges generated in a photosensitive matrix or photosensitive linear array.

Abstract: An integrated semiconductor circuit made up of a differential stage which comsists of a differential pair of field effect transistors (10, 11) having outputs (34, 35) which are coupled to the inputs of an output stage or sub-circuit (31, 32, 51, 52) for controlling same, and also including a load circuit (R.sub.4, R.sub.3). The circuit provides smoothing means for smoothing fluctuations of an output impedance of the differential transistor pair (10,11) during switching thereof.

Abstract: An integrated circuit, D-type master-slave flipflop includes a bistable master element connected between two supply voltage terminals and having a first data input for receiving data. A control means is provided having a control signal input for erasing or writing into the master element under the control of a control signal. A bistable slave element is connected between the two supply voltage terminals and has a second data input connected to a data output of the master element. The slave element is directly controlled by signals on the second data input for enabling writing into the slave element after an output signal at the master element data output reaches a predetermined voltage level.

Abstract: A monolithic integrated memory includes a differential read amplifier circuit which is associated with a column of the memory and which has two source-coupled field effect transistors, the coupling point of which is controlled by a current source which itself is controlled by the output signal of a decoder stage which enables the selection of the memory column. The gate of each coupled transistor receives the signal of a bit line of the memory column, while the drains of the coupled transistors apply a signal to the read bus of the memory. A translator circuit is provided for translating the levels of the signals transported by the bit lines in order to ensure that these levels are at most equal to the levels of the signals transported by the read bus, so that the gate-drain capacitances of the coupled transistors of the differential amplifier are negligibly small.