Abstract: An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.

Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.

Abstract: The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.

Abstract: An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.

Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.

Abstract: An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.

Abstract: A time base circuit, for an oscillator and apparatus, defines a time interval in terms of a time taken for a capacitor to charge from a reference voltage level to a detection voltage level. The circuit operates by: supplying at the start of the interval a capacitor charging current, using a first semiconductor device supplied from a first power supply voltage, the device delivering the charging current according to a predetermined dependency on the first power supply voltage; and identifying the detection voltage level to signal the end of the time interval, using a second semiconductor device supplied from the first power supply voltage, the second semiconductor device identifying the detection voltage level value according to the same predetermined dependency on the first power supply voltage as for the first semiconductor device, the time interval being made substantially independent of variations of the first power supply voltage.

Abstract: The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.

Abstract: A time base circuit, for an oscillator and apparatus, defines a time interval in terms of a time taken for a capacitor to charge from a reference voltage level to a detection voltage level. The circuit operates by: supplying at the start of the interval a capacitor charging current, using a first semiconductor device supplied from a first power supply voltage, the device delivering the charging current according to a predetermined dependency on the first power supply voltage; and identifying the detection voltage level to signal the end of the time interval, using a second semiconductor device supplied from the first power supply voltage, the second semiconductor device identifying the detection voltage level value according to the same predetermined dependency on the first power supply voltage as for the first semiconductor device, the time interval being made substantially independent of variations of the first power supply voltage.

Abstract: An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.

Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.

Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.

Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.

Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.

Abstract: A neutralization device to reset or inhibit at least certain electronic functions of an integrated circuit depending on the level of the supply voltage Vdd comprises a conditional feedback means to deactivate it especially in standby mode and then eliminate its consumption, and to reactivate it for certain modes of operation of the integrated circuit.