Patents by Inventor Thierry Giovinazzi

Thierry Giovinazzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7869268
    Abstract: An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: January 11, 2011
    Assignee: STMicroelectronics SA
    Inventors: Thierry Giovinazzi, Francesco La Rosa
  • Patent number: 7599218
    Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics SA
    Inventors: Christophe Rodat, Thierry Giovinazzi
  • Patent number: 7529145
    Abstract: The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: May 5, 2009
    Assignee: STMicroelectronics SA
    Inventors: Francesco La Rosa, Thierry Giovinazzi
  • Patent number: 7454644
    Abstract: An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: November 18, 2008
    Assignee: STMicroelectronics SA
    Inventors: Thierry Giovinazzi, Filipe Ganivet
  • Publication number: 20080062752
    Abstract: An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 13, 2008
    Applicant: STMICROELECTRONICS SA
    Inventors: Thierry Giovinazzi, Francesco La Rosa
  • Publication number: 20080062806
    Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 13, 2008
    Applicant: STMICROELECTRONICS SA
    Inventors: Christophe Rodat, Thierry Giovinazzi
  • Patent number: 7026882
    Abstract: A time base circuit, for an oscillator and apparatus, defines a time interval in terms of a time taken for a capacitor to charge from a reference voltage level to a detection voltage level. The circuit operates by: supplying at the start of the interval a capacitor charging current, using a first semiconductor device supplied from a first power supply voltage, the device delivering the charging current according to a predetermined dependency on the first power supply voltage; and identifying the detection voltage level to signal the end of the time interval, using a second semiconductor device supplied from the first power supply voltage, the second semiconductor device identifying the detection voltage level value according to the same predetermined dependency on the first power supply voltage as for the first semiconductor device, the time interval being made substantially independent of variations of the first power supply voltage.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: April 11, 2006
    Assignee: STMicroelectronics SA
    Inventors: Philippe Ganivet, Thierry Giovinazzi, Francois Tailliet
  • Publication number: 20060067129
    Abstract: The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 30, 2006
    Applicant: STMicroelectronics SA
    Inventors: Francesco La Rosa, Thierry Giovinazzi
  • Publication number: 20050062519
    Abstract: A time base circuit, for an oscillator and apparatus, defines a time interval in terms of a time taken for a capacitor to charge from a reference voltage level to a detection voltage level. The circuit operates by: supplying at the start of the interval a capacitor charging current, using a first semiconductor device supplied from a first power supply voltage, the device delivering the charging current according to a predetermined dependency on the first power supply voltage; and identifying the detection voltage level to signal the end of the time interval, using a second semiconductor device supplied from the first power supply voltage, the second semiconductor device identifying the detection voltage level value according to the same predetermined dependency on the first power supply voltage as for the first semiconductor device, the time interval being made substantially independent of variations of the first power supply voltage.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 24, 2005
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Philippe Ganivet, Thierry Giovinazzi, Francois Tailliet
  • Publication number: 20040255208
    Abstract: An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.
    Type: Application
    Filed: July 30, 2004
    Publication date: December 16, 2004
    Inventors: Thierry Giovinazzi, Filipe Ganivet
  • Patent number: 6829169
    Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: December 7, 2004
    Assignee: STMicroelectronics SA
    Inventors: Filipe Ganivet, Francesco La Rosa, Thierry Giovinazzi
  • Patent number: 6812747
    Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics SA
    Inventors: Filipe Ganivet, Francesco La Rosa, Thierry Giovinazzi
  • Publication number: 20040032243
    Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.
    Type: Application
    Filed: April 22, 2003
    Publication date: February 19, 2004
    Applicant: STMicroelectronics SA
    Inventors: Filipe Ganivet, Francesco La Rosa, Thierry Giovinazzi
  • Publication number: 20030223289
    Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.
    Type: Application
    Filed: April 22, 2003
    Publication date: December 4, 2003
    Applicant: STMicroelectronics SA
    Inventors: Filipe Ganivet, Francesco La Rosa, Thierry Giovinazzi
  • Patent number: 6157227
    Abstract: A neutralization device to reset or inhibit at least certain electronic functions of an integrated circuit depending on the level of the supply voltage Vdd comprises a conditional feedback means to deactivate it especially in standby mode and then eliminate its consumption, and to reactivate it for certain modes of operation of the integrated circuit.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 5, 2000
    Assignee: SGS-Thomson Microelectronics SA
    Inventors: Thierry Giovinazzi, David Naura