Abstract: The invention concerns a memory cell insensitive to disturbances. The memory cell, that contains information in the form of two complementary logical levels (X, C(X)), each logical level being stored in a node of the cell (N1, N2), is characterized in that it comprises means of storing the same logical level in two different nodes (N1, N2, N3, N4), the said means being able to restore any logical level to its initial state preceding a modification made on it due to a disturbance, as a result of holding the value of one of the two logical levels complementary to the logical level that was modified.

Abstract: Disclosed is an analog/digital converter designed to convert an analog voltage into a digital voltage with n bits. The converter comprises:p=2.sup.n comparators capable of comparing the analog voltage with a reference analog voltage obtained by a voltage generator, each comparator comprising an inverter amplifier, a capacitor having a first terminal connected to the input of the amplifier and wherein, before the application of the analog voltage, each amplifier is connected in short-circuit feedback loop while the reference voltage is applied to the other terminal of the capacitor, this operation being performed no longer in parallel for all the amplifiers but successively, one after another in order to reduce the consumption of current during this operation.