Abstract: Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a type of access and designating one or several memory locations (46a-d, 47a-b) arranged in accordance with a sequence suitable for said request, processing the requests in accordance with a successive sequence so as to transfer, for each processed request, data from the designated memory location to the data processing circuit, or vice versa, the processing of a request (46) designating memory locations (46a, 46b, 46c, 46d) associated with several banks (A, B, A, B) authorizing a transfer of data between the interface and the memory locations in a sequence which is different from the sequence associated with said request.

Abstract: A functional system comprises a set of functions (F) requiring access to a collective resource (RSRC). Such a system can be, for example, a data processing system comprising a plurality of processors requiring access to a collective memory. For reasons of cost it is desirable to guarantee a certain minimum access for one or more functions while a certain degree of flexibility as regards the access is maintained. For this purpose, the system comprises an interface (INT) adapted to implement an access scheme (AS) characterized by a plurality of states (S) passed through in a predetermined manner. A state (S) forms a possibility of access of a given length and defines an order of priority in accordance with which a function (F) can access the collective resource (RSRC).

Abstract: A processing of data in cooperation with a memory (MEM), for example an MPEG decoding, has the following characteristic features. A processor (P) generates a logic request (LRQ). The logic request (LRQ) defines at least one characteristic (CAR) common to a group of data (GRP). An addressing circuit (AGA) generates a physical request (PRQ) on the basis of the logic request (LRQ). The physical request (PRQ) defines memory (MEM) addresses (A) relating to the group of data (GRP). A memory interface (INT) effects a transfer (TRNSFR) of the group of data (GRP) between the memory (MEM) and the processor (P) on the basis of the physical request (PRQ). Thus, the processor need not know how and where the data to be processed or having been processed are stored in the memory. This facilitates the design of a data processing device and, particularly, a family of such devices.

Abstract: Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of:

Abstract: A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

Abstract: A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.