Abstract: A method for manufacturing an integrated circuit includes the steps of: forming above an upper surface of a substrate (5) at least one dielectric layer (15) extending on an underlying surface (12), the dielectric layer (15) having an upper surface (25) and a flank (40) extending between the upper surface and the underlying surface (12); and forming an electrical structure (70) in one piece in an electrically conducting material including a structural element (75) extending on the upper surface (25) of the dielectric layer (15) and an interconnection element (80) extending from the structural element (75) along the flank (40) as far as the underlying surface. The flank has a height of more than 10 ?m, and the electrical structure is formed by depositing the electrically conducting material by simultaneously depositing the structural element on the upper surface of the dielectric layer and the interconnection element on the flank.

Abstract: An envelope (100) detector for detecting a modulation envelope of a modulated signal. The envelope detector includes a sensor (102). The sensor has a sensor input (1021), for sensing a signal forming a measure for the amount of electrical power presented at the sensor input (1021). The sensor input (1021) is electrically conducting connectable to an electrical path (14), along which electrical path (14) the modulated signal is transmitted. The detector (100) includes a filter (103) for removing from the sensed signal a part contributed to non-envelope signal components in the modulated signal; and a detector output (104) connected to the filter (103) for outputting an envelope signal.

Abstract: A balanced and active coplanar microwave coupler for an MMIC, comprising FETs provided with metal grid, source, and drain electrodes integrated with coplanar plane metal elements combined to constitute the inlet and outlet accesses of the coupler. All of the access are constituted by an association comprising one or more CPSes and one or more CPWs.

Abstract: A limiter circuit having a field effect transistor whose bias circuit is constituted by two constant voltage feeds: one for its gate and the other for its drain, with a resistive load being connected in series with the feed to the gate of the transistor. The invention is particularly applicable to space telecommunications.