Patents by Inventor Thierry Parrassin

Thierry Parrassin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9903824
    Abstract: An apparatus and method for optical probing of a DUT is disclosed. The system enables identifying, localizing and classifying faulty devices within the DUT. A selected area of the DUT is imaged while the DUT is receiving test signals, which may be static or dynamic, i.e., causing certain of the active devices to modulate. Light from the DUT is collected and is passed through a transparent diffracting grating prior to imaging it by a sensor and converting it into an electrical signal. The resulting image includes the zero order and first order diffraction of the grating. The grating is configured such that the zero order is in registration with emission sites imaged when the grating is outside the optical path.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 27, 2018
    Assignee: FEI EFA, Inc.
    Inventors: Herve Deslandes, Antoine Reverdy, Thierry Parrassin
  • Publication number: 20150293037
    Abstract: An apparatus and method for optical probing of a DUT is disclosed. The system enables identifying, localizing and classifying faulty devices within the DUT. A selected area of the DUT is imaged while the DUT is receiving test signals, which may be static or dynamic, i.e., causing certain of the active devices to modulate. Light from the DUT is collected and is passed through a transparent diffracting grating prior to imaging it by a sensor and converting it into an electrical signal. The resulting image includes the zero order and first order diffraction of the grating. The grating is configured such that the zero order is in registration with emission sites imaged when the grating is outside the optical path.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 15, 2015
    Inventors: Herve Deslandes, Antoine Reverdy, Thierry Parrassin
  • Patent number: 9000790
    Abstract: A method can be used for detecting defects in an electronic integrated circuit that includes a power input and a data input. The electronic integrated circuit is powered with a periodic power signal having a frequency and an input signal is applied to the data input. A surface of the electronic integrated circuit is swept with a laser beam. A first image is generated using a laser beam reflected from the surface and a second image is generated using a selected part of the laser beam reflected from the surface. The selected part of the reflected laser beam has a frequency that corresponds to the frequency of the power signal. Defects in the integrated circuit can be detected by superposing the first image and the second image.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics SA
    Inventors: Guillaume Celi, Thierry Parrassin, Sylvain Dudit
  • Publication number: 20130002283
    Abstract: A method can be used for detecting defects in an electronic integrated circuit that includes a power input and a data input. The electronic integrated circuit is powered with a periodic power signal having a frequency and an input signal is applied to the data input. A surface of the electronic integrated circuit is swept with a laser beam. A first image is generated using a laser beam reflected from the surface and a second image is generated using a selected part of the laser beam reflected from the surface. The selected part of the reflected laser beam has a frequency that corresponds to the frequency of the power signal. Defects in the integrated circuit can be detected by superposing the first image and the second image.
    Type: Application
    Filed: August 6, 2012
    Publication date: January 3, 2013
    Applicant: STMICROELECTRONICS SA
    Inventors: Guillaume Celi, Thierry Parrassin, Sylvain Dudit
  • Publication number: 20060157699
    Abstract: A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and the front side of the integrated circuit. This tunnel is designed to channel photons emitted by the switching element towards the front side.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 20, 2006
    Applicant: STMicroelectronics SA
    Inventors: Michel Vallet, Philippe Sardin, Thierry Parrassin, Sylvain Dudit
  • Patent number: 7026198
    Abstract: A buried oxide layer of an SOI substrate beneath a structure electrically isolated from the rest of a semiconductor device is made to break down so as to open a bias path for the substrate through the structure. It then suffices to connect the electrical ground of the semiconductor device to this bias path so that the ions flow away into the substrate during a focused ion beam treatment of the semiconductor device.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: April 11, 2006
    Assignee: STMicroelectronics S.A.
    Inventor: Thierry Parrassin
  • Publication number: 20040266072
    Abstract: A buried oxide layer of an SOI substrate beneath a structure electrically isolated from the rest of a semiconductor device is made to break down so as to open a bias path for the substrate through the structure. It then suffices to connect the electrical ground of the semiconductor device to this bias path so that the ions flow away into the substrate during a focused ion beam treatment of the semiconductor device.
    Type: Application
    Filed: February 19, 2004
    Publication date: December 30, 2004
    Applicant: STMICROELECTRONICS SA
    Inventor: Thierry Parrassin