Patents by Inventor Thierry Simon

Thierry Simon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12381729
    Abstract: A device multiplies a first public key by a first scalar value, generating an intermediate result. The first public key corresponds to a point on an elliptic curve of order n, n is an integer, and the first scalar value is equal to n/m where in is a largest prime integer factor of n. The device determines whether the intermediate result is equal to a value corresponding to a point O at infinity on the elliptic curve. In response to the determining indicating the intermediate result is different from the value corresponding to the point O, the device multiplies the intermediate result by a second scalar, generating a shared secret value. The device performs one or more processing operations using the generated shared secret value. Otherwise, the device may initiate error processing without generating the shared secret value.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: August 5, 2025
    Assignee: STMICROELECTRONICS BELGIUM
    Inventors: Thierry Simon, Gilles Van Assche
  • Publication number: 20250080316
    Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may compute Hamming weight of a bit string.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Thierry SIMON, Ronny VAN KEER
  • Publication number: 20240281214
    Abstract: A method includes performing a cryptographic operation using a processing device. The performing the cryptographic operation includes protecting the performing of the cryptographic operation against side channel attacks by selecting a value amongst two values based on a selection bit. Selecting the value includes concatenating the two values in a register, generating a concatenated word including the two values in two distinct portions of the concatenated word in the register. The concatenated word is rotated according to the value of the selection bit to position the selected value in a determined portion of the concatenated word in the register amongst said two portions. The unselected value in the concatenated word is suppressed. One or more processing operations is performed based on a result of the cryptographic operation.
    Type: Application
    Filed: February 12, 2024
    Publication date: August 22, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Thierry SIMON
  • Patent number: 11831771
    Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: ? i ? [ 1 ; N ] ? { r ? ( l ) = ? j = 1 K A ? ( i , j ) * p ? ( j ) R ? ( i ) = ? j = 1 K A ? ( i , j ) * P ? ( j ) , wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 28, 2023
    Assignees: STMICROELECTRONICS S.r.l., PROTON WORLD INTERNATIONAL N.V.
    Inventors: Thierry Simon, Michael Peeters, Francesco Caserta
  • Publication number: 20230299957
    Abstract: A device multiplies a first public key by a first scalar value, generating an intermediate result. The first public key corresponds to a point on an elliptic curve of order n, n is an integer, and the first scalar value is equal to n/m where in is a largest prime integer factor of n. The device determines whether the intermediate result is equal to a value corresponding to a point O at infinity on the elliptic curve. In response to the determining indicating the intermediate result is different from the value corresponding to the point O, the device multiplies the intermediate result by a second scalar, generating a shared secret value. The device performs one or more processing operations using the generated shared secret value. Otherwise, the device may initiate error processing without generating the shared secret value.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 21, 2023
    Applicant: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Thierry SIMON, Gilles VAN ASSCHE
  • Publication number: 20220141016
    Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: ? ? i ? [ 1 ; N ] ? { r ? ( l ) = ? j = 1 K ? A ? ( i , j ) * p ? ( j ) R ? ( i ) = ? j = 1 K ? A ? ( i , j ) * P ? ( j ) , wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.
    Type: Application
    Filed: October 20, 2021
    Publication date: May 5, 2022
    Applicants: STMICROELECTRONICS S.r.l., PROTON WORLD INTERNATIONAL N.V.
    Inventors: Thierry SIMON, Michael PEETERS, Francesco CASERTA
  • Patent number: 9608653
    Abstract: A device can be used for compensating bandwidth mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 28, 2017
    Assignee: STMicroelectronics SA
    Inventors: Nicolas Le Dortz, Thierry Simon, Pascal Urard, Caroline Lelandais-Perrault, Rakhel Kumar Parida
  • Publication number: 20170026052
    Abstract: A device can be used for compensating bandwith mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.
    Type: Application
    Filed: November 21, 2014
    Publication date: January 26, 2017
    Inventors: Nicolas Le Dortz, Thierry Simon, Pascal Urard, Caroline Lelandais-Perrault, Rakhel Kumar Parida
  • Patent number: 8890728
    Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M?1 trains involves respectively M?1 second signals gleaned from the derived signal and the suite of M?1 shift coefficients.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics SA
    Inventors: Nicolas Le Dortz, Thierry Simon, Pascal Urard, Caroline Lelandais-Perrault
  • Publication number: 20140232575
    Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M?1 trains involves respectively M?1 second signals gleaned from the derived signal and the suite of M?1 shift coefficients.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 21, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Nicolas Le Dortz, Thierry Simon, Pascal Urard, Caroline Lelandais-Perrault