Abstract: A synchronization aid device is part of receiving communication equipment of an IP network, having a primary clock signal consisting of primary clock pulses spaced apart by a first period. This device comprises i) a required to increment its value by one unit on each primary clock pulse and reset its value to zero each time it reaches a value M, ii) detection means required to generate a secondary clock pulse each time the value of the counter is zero, the secondary clock pulses forming a secondary clock signal having a second period equal to M times the first period, and iii) control means required, each time the receiving equipment receives a packet containing at least one first bit having a first value, to initialize the counter with a chosen value.

Abstract: The invention concerns a device able for receiving packets in a packet communication network comprising at least two stations, characterized in that it includes: phase-locked loop, as well as means for: receiving packets containing samples of said network, said samples being derived from data sampled every Tech period, where Tech is derived from a time base synchronized on all the stations of said network and said samples being associated with incremental values predicting at least one sample, calculating, in case of interruption of packet reception, a prediction of a sample that should have been received, by adding an increment value to a received sample value. The invention also concerns a device for transmitting packets in a packet communication network.

Abstract: The invention concerns device for transmitting packets in a packet communication network comprising at least two stations, including in particular means for generating a first temporal descriptor from a sampled value of a master counter, means for generating a second temporal descriptor from a sampled value of a second counter synchronized on all the network stations and means for transmitting jointly the two temporal descriptors in the network. The invention also concerns a device for receiving packets in a packet communication network, which uses the double temporal descriptor generated by the transmitter device.

Abstract: The invention concerns a method for-transmitting digital television services via a gateway suitable to receive several digital multiplexes, each multiplex comprising at least one digital audiovisual service, the gateway being capable of receiving a limited number of multiplexes among the said plurality and of transmitting them to at least one terminal. In order to improve access to the service when the gateway reaches its capacity limit, the gateway transmits a list of at least one available service, to at least one of the terminals; the available services being present on the multiplexes, that the gateway can receive depending on the possible services already transmitted to at least one of the said terminals.

Abstract: A device (D2) is dedicated to the reconstruction of clock signals, for example within communication equipment (EQ2) of an IP network. This device (D2) comprises i) a phase-locked loop (BV) having a cut-off frequency dependent, on the one hand, on a configuration value making it possible to reconstruct clock signals according to a chosen clock frequency, and on the other hand, a chosen sampling frequency, and ii) control means (MC2) responsible for forcing the phase-locked loop (BV) to present a variable cut-off frequency according to a received operating mode indication.

Abstract: A device (DA1) is intended to aid a clock synchronization device (DS1) of a master station (SM) of a wireless network in performing time synchronizations, this master station (SM) comprising a master clock (HM) represented by the value of a master counter (CM) and means (MG1) for generating wireless frames of IP packets containing in particular PTP messages of first and second types.

Abstract: A device is dedicated to assisting the reconstruction of synchronization signals, for example within an item of communication equipment of an IP network. This device comprises i) a phase-locked loop charged with reconstructing, on the basis of a second sampled ramp signal received, a reference clock signal and a second ramp signal identical to, and in phase with, that having been sampled, and ii) processing means charged with determining in a first sampled ramp signal received, representative of a synchronization signal to be reconstructed and each sample of which is associated with a sample of the second ramp signal corresponding to a determinable sampling period, the value which corresponds to the first sample of this first sampled ramp signal received as well as the sampling period corresponding to this value, and then to initialize with this value a synchronization counter which is synchronized with respect to the second reconstructed ramp signal, on the basis of the reconstructed reference clock signal.

Abstract: A process for transmitting data in a network adapted for isochronous and asynchronous transmissions and comprising a sender and at least one receiver.

Abstract: The subject of the invention is a process for transmitting data in a network adapted for isochronous and asynchronous transmission and comprising a sender and at least one receiver.

Abstract: The invention relates to a device for transferring data packets between two data networks comprising

Abstract: The invention concerns a method for handling isochronous files in a HAVi network.

Abstract: A process of clock recovery during the sampling of computer-type signals, wherein the sampling clock is generated from a phase locked loop or PLL which multiplies a given frequency by an integer number, includes gauging the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the said signals in such a way as to obtain a first position-dependent value, carrying out a sampling clock phase correction and then carrying out a sampling clock frequency correction by using a processor.