Abstract: There is described a multimodule data processing system with N fully interconnected data processing modules for executing a Dispersed Joined Communication method according to a K-level nested and level-wise compartimentalized encoding, broadcasting and decoding operation. This allows for protecting against at most T maliciously operating modules, wherein K=T+1. At level K all said N modules are situated in a single compartment. At level k=1 for any extant message in any actual module such extant message is broadcast to all modules present in that message's compartment. For any level K+1>k>1 said operation previously comprises for any extant message generating therefrom n>2T symbols according to a T-symbol error correcting encoding and within that message's actual compartment transmitting each of such n symbols as messages to a respective different module. Those different modules together constitute a next lower-level compartment for therein executing said operation according to next lower level k-1.

Abstract: A multiprocessor computer system consists of n computer modules. Each computer module includes a processor module and a reducing encoder for forming a data word from a code symbol. The code symbols are broadcast to all computer modules for further processing, so that a correct data word comprising k symbols can be reconstructed by means of a symbol-correcting code, while at the most t code symbols may be disturbed. For the connection of an external apparatus, the latter transmits A original versions to a corresponding number of computer modules. The original versions are broadcast to the computer modules as secondary, tertiary, . . . versions during successive broadcast steps. Subsequently, decision steps are taken in the opposite sense, that is to say during a last step but one in majority decision is taken each time on the basis of a secondary version and the tertiary versions originating from the same original version as the relevant secondary version.

Abstract: A multiprocessor computer system having n parallel-operating computer modules which each include a processor module, a memory module and a data word reconstruction module, wherein each module of said system processes the same piece of data simultaneously and in parallel. The data words are applied to a reducing encoder so that code symbols stored in the relevant computer modules form a code word. The relevant error-correction code has a simultaneous correction capability in at least two code symbols. Each data word reconstruction module receives the entire code word in order to reconstruct the data word therefrom. Each computer module also has an input/output memory module. This module receives a coded data word which is decoded when it is presented again. Decoding is performed so that each bit in the input/output memory is mapped on at the most one bit of the associated memory module.

Abstract: A time division switching system to which incoming and outgoing transmission channels designed for the transmission of bit streams subdivided into bits are connected.

Abstract: A computer system based on a symbol-correcting code. The code words consist of a number of code symbols. In the normal operating mode of the error correction members, correction is possible of all errors which are either limited to one code symbol or which concern only two arbitrarily situated code bits. During operation in the erasure mode, a predetermined code symbol within the code word is not taken into account; therefore, it may contain an arbitrary, unknown error. An error can be corrected which concerns only one arbitrarily situated code bit. In the selection mode, two predetermined code symbols within the code word are not taken into account. The data words can be reconstructed from the others. The mode is controlled by the content of the mode register. The mode register is controlled by the output signals of syndrome generators.

Abstract: A system for correcting multiple simultaneously erroneous channels within a plurality of parallel data channels including redundant channels. At the receiving side a group of syndrome generators each applies a secondary parity check matrix for producing corresponding groups of syndrome bit streams. If the error is correctable, one or more of the syndrome bit streams is added to corresponding code bit streams. If a syndrome bit stream indicates an error in a non-applicable code bit channel, or otherwise indicates too many errors, it remains unused. Decoders with feedback (restoration of syndromes after correction) and feedback-free decoders are possible.

Abstract: A multiprocessor computer system is distributed over error isolation areas, each of these areas containing a processor element, an encoder, a section of a memory and an information reconstruction section which are connected in this order in a cyclic path. The processor elements work in parallel on the same data word, which has a certain length. When the result of the processing has to be stored in the memory, each encoder forms a code symbol of shorter length, on the basis of the data word. The set of code symbols formed on the basis of the data word forms a code word with a larger bit length than the data word mentioned. By means of an error correcting code at least one erroneous code symbol in the code word can be corrected. The code symbols are stored in the respective memory sections. If the data word concerned has to be further processed, all corresponding code symbols are fed to all information reconstruction sections.

Abstract: An error correction device for digital data storage and transfer systems wherein data are transferred over a plurality of channels. Synchronously with the transfer of a group of data bits, a coding device forms a first correction bit for a first correction channel and a second correction bit for a second correction channel. The first correction bit is formed on the basis of a second group of data bits, the second correction bits being formed on the basis of a third group of data bits. Each data channel supplies the data of two sub-groups of data bits for this purpose. The delay operator having a length of one bit cell being represented by D, a series of directly successive bits can be represented by a polynomial in D: x0.D.sup.0 +x1.D.sup.1 +x2.D.sup.2 + . . ., in which xj (j =0, 1 . . .) represents the bit value.

Abstract: A memory in which each word location for a user word not only contains the bit locations for the actual data but also one parity bit for the parity over the entire word location and one correction bit. A fixed number of word locations are grouped to form a memory location for the storage of a memory word. When a word location is read by a data user, the parity bit indicates whether the word location contains none or one bit error. If the user word contains an error, the other word locations of the same memory location and also the associated correction bits are read to correct one arbitrary bit error in the memory word. In given cases, a plurality of bit errors can be corrected if they are situated in bit positions of the same rank within the word locations for the user words. The chance that a multiple error has exactly this configuration can be enhanced by a suitable arrangement of the bit locations in a memory. Thus, a limited amount of redundancy suffices in many cases.