Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.

Abstract: A semiconductor assembly, power semiconductor module, a housing and methods for assembling the power semiconductor housing is disclosed. One embodiment provides an electrically insulating substrate has an inner housing having a cover and a peripheral rim, and at least one pressure element arranged adjacent a side-face of the peripheral rim. The pressure element is resiliently coupled to the inner housing.

Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.

Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.

Abstract: A pressure contact arrangement includes a pressure contact device having an upper contact piece and a lower contact piece, one or more vertical first semiconductor chips and a peripherally closed adhesive bead. Each vertical first semiconductor chip has an upper side, a lower side opposite the upper side, a peripherally closed narrow side adjoining the upper side and the lower side and connecting the upper and lower sides, an upper electrical contact face arranged on the upper side, and a lower electrical contact face arranged on the lower side. The peripherally closed adhesive bead surrounds each vertical first semiconductor chip and fastens each vertical first semiconductor chip to the pressure contact device. A peripherally closed connecting face is provided between each adhesive bead and the narrow side of the corresponding vertical first semiconductor chip that laterally surrounds the vertical first semiconductor chip.

Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.

Abstract: A semiconductor module system includes a substrate, at least one semiconductor chip, and a number of at least two electrically conductive first connecting elements. The substrate has a bottom side and a top side spaced apart from the bottom side in a vertical direction. The at least one semiconductor chip is arranged on the top side. Each one of the first connecting elements has a first end which protrudes away from an insulation carrier of the substrate in a direction perpendicular to the vertical direction. The semiconductor system further includes a connecting system with a number of N?1 connectors. A first one of the connectors includes at least two electrically conductive second connecting elements. Each one of the second connecting elements has a first end. The first end of each one of the first connecting elements is electrically conductively connectable to the first end of one of the second connecting elements.

Abstract: A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: A pressure contact arrangement includes a pressure contact device having an upper contact piece and a lower contact piece, one or more vertical first semiconductor chips and a peripherally closed adhesive bead. Each vertical first semiconductor chip has an upper side, a lower side opposite the upper side, a peripherally closed narrow side adjoining the upper side and the lower side and connecting the upper and lower sides, an upper electrical contact face arranged on the upper side, and a lower electrical contact face arranged on the lower side. The peripherally closed adhesive bead surrounds each vertical first semiconductor chip and fastens each vertical first semiconductor chip to the pressure contact device. A peripherally closed connecting face is provided between each adhesive bead and the narrow side of the corresponding vertical first semiconductor chip that laterally surrounds the vertical first semiconductor chip.

Abstract: In a method for producing a power semiconductor arrangement, a dielectric insulation carrier with a top side and a top metallization layer arranged on the top side are provided. Also provided are a semiconductor chip and at least one electrically conductive contact pin, each pin having a first end and an opposite second end. The semiconductor chip is sintered or diffussion soldered to the top metallization layer. Between the first end and the top metallization layer an electrically conductive connection is formed, in which electrically conductive connection material of the contact pin is in direct physical contact with the material of the top metallization layer.

Abstract: The invention relates to a power semiconductor module including a module underside, a module housing, and at least two substrates spaced from each other. Each substrate has a topside facing an interior of the module housing and an underside facing away from the interior of the module housing. The underside of each substrate includes at least one portion simultaneously forming a portion of the module underside. At least one mounting means disposed between two adjacent substrates enables the power semiconductor module to be secured to a heatsink.

Abstract: A power semiconductor module includes a module housing with a sealing ring on its top side. The sealing ring, in co-operation with the module housing and a printed circuit board attached to the power semiconductor module, hermetically seals feed-through locations at the top side of the module housing for feeding through electric terminals of the power semiconductor module. On the bottom side of the module housing a sealing ring hermetically seals the bottom side of the module housing.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: In a method for producing a power semiconductor arrangement, a dielectric insulation carrier with a top side and a top metallization layer arranged on the top side are provided. Also provided are a semiconductor chip and at least one electrically conductive contact pin, each pin having a first end and an opposite second end. The semiconductor chip is sintered or diffussion soldered to the top metallization layer. Between the first end and the top metallization layer an electrically conductive connection is formed, in which electrically conductive connection material of the contact pin is in direct physical contact with the material of the top metallization layer.

Abstract: A power semiconductor module includes a package having a first package portion and a second package portion. The side of the first package portion facing the second package portion has an anchoring element with a first recess. The second package portion includes a second recess with an indentation which receives the anchoring element. To produce a mechanically firm connection between the first package portion and the second package portion, a plug-in element is inserted in the first recess and the second recess. The plug-in element displaces the anchoring element transversely with respect to the plug-in direction, causing the anchoring element to engage the indentation so that a form-fit connection is produced between the first package portion and the second package portion. The plug-in element prevents the anchoring element from disengaging the indentation.

Abstract: A semiconductor module system includes a substrate, at least one semiconductor chip, and a number of at least two electrically conductive first connecting elements. The substrate has a bottom side and a top side spaced apart from the bottom side in a vertical direction. The at least one semiconductor chip is arranged on the top side. Each one of the first connecting elements has a first end which protrudes away from an insulation carrier of the substrate in a direction perpendicular to the vertical direction. The semiconductor system further includes a connecting system with a number of N?1 connectors. A first one of the connectors includes at least two electrically conductive second connecting elements. Each one of the second connecting elements has a first end. The first end of each one of the first connecting elements is electrically conductively connectable to the first end of one of the second connecting elements.

Abstract: The invention relates to a power semiconductor module including a power semiconductor chip arranged on a substrate and comprising a bottom side facing the substrate, a top side facing away from the substrate, and an electrical contact face arranged on the top side. A bond wire is bonded to the contact face. At least when the power semiconductor module is fastened to a heatsink, a contact pressure element creates a contact pressure force (F) acting on a sub-portion 36 of a bond wire portion configured between two adjacent bond sites. The contact pressure force (F) results in the power semiconductor chip and a substrate beneath being pressed against the heatsink.

Abstract: A power semiconductor arrangement and method is disclosed. One embodiment provides a power semiconductor module. An insulator is arranged between the module and a cooling element, increasing clearances between the power semiconductor module and the cooling element.