Abstract: An interface module for a communications system includes a processing device and a peripheral device which are interconnected through a communications bus. The interface module includes a transceiver interface and a protection circuit. The protection circuit is positioned between the transceiver interface and a port configured to receive a signal from a terminal of the communications bus. The protection circuit is further configured to automatically provide a protection voltage to the transceiver interface if a power supply for the transceiver interface is inactive. The protection voltage is derived from the signal received at the terminal.

Abstract: A high speed high capacity SRAM having a density of 256K bits or larger. Individual complementary memory cell pairs are arranged in memory blocks and are directly accessed during write and read operations by input/output circuitry having an input buffer, write driver circuits, sense amplifiers, an output buffer and an output register. Data is read from individual memory blocks using a pipelined read data mode in which data accessed by a row, column and block address during a first cycle is stored in an output (pipeline) register at the beginning of the next cycle. In one embodiment all components of the data input/output circuits are located remotely from the memory blocks and paired data lines are used.

Abstract: A synchronous SRAM (or DRAM or other logic) chip with input registers (or latches) associated with the chip memory cell array input lines, where there is logic associated with the registers, locates the logic gates upstream of the registers and connected to the D input of each register. Hence the logic gates not only provide the needed logic function, but also provide the necessary delay to meet the specified hold time delay in synchronous circuits. This reduces the logic function after the input registers and hence improves the clock-to-output access time of the chip.