Abstract: A memory device includes a memory array and a memory controller operatively coupled to the memory array. The memory array includes memory cells to store memory data. The memory controller includes a prefetch buffer, a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, and logic circuitry. The logic circuitry is configured to store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer, and omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer.

Abstract: A memory device includes a memory array and a memory controller operatively coupled to the memory array. The memory array includes memory cells to store memory data. The memory controller includes a prefetch buffer, a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, and logic circuitry. The logic circuitry is configured to store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer, and omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer.

Abstract: A processor system includes a processor core, a cache, a cache controller, and a cache assist controller. The processor core issues a read/write command for reading data from or writing data to a memory. The processor core also outputs an address range specifying addresses for which the cache assist controller can return zero fill, e.g., an address range for the read/write command. The cache controller transmits a cache request to the cache assist controller based on the read/write command. The cache assist controller receives the address range output by the processor core and compares the address range to the cache request. If a memory address in the cache request falls within the address range, the cache assist controller returns a string of zeroes, rather than fetching and returning data stored at the memory address.

Abstract: A processor system includes a processor core, a cache, a cache controller, and a cache assist controller. The processor core issues a read/write command for reading data from or writing data to a memory. The processor core also outputs an address range specifying addresses for which the cache assist controller can return zero fill, e.g., an address range for the read/write command. The cache controller transmits a cache request to the cache assist controller based on the read/write command. The cache assist controller receives the address range output by the processor core and compares the address range to the cache request. If a memory address in the cache request falls within the address range, the cache assist controller returns a string of zeroes, rather than fetching and returning data stored at the memory address.