Patents by Inventor Thiruvengadam Vijayaraghavan

Thiruvengadam Vijayaraghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mechanism for reducing page migration overhead in memory systems
    Patent number: 10339067
    Abstract: A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 2, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yasuko Eckert, Thiruvengadam Vijayaraghavan, Gabriel H. Loh
  • MECHANISM FOR REDUCING PAGE MIGRATION OVERHEAD IN MEMORY SYSTEMS
    Publication number: 20180365167
    Abstract: A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Yasuko Eckert, Thiruvengadam Vijayaraghavan, Gabriel H. Loh