Abstract: A seal arrangement is provided for sealing an exposed edge of a composite laminate part having a fay surface configured to be joined to a structure. The seal arrangement includes a precured edge seal covering the exposed edge and a cover covering the edge seal. A seal bead located within a recess in the fay surface of the part forms a seal between the part and the structure.

Abstract: A seal arrangement is provided for sealing an exposed edge of a composite laminate part having a fay surface configured to be joined to a structure. The seal arrangement includes a precured edge seal covering the exposed edge and a cover covering the edge seal. A seal bead located within a recess in the fay surface of the part forms a seal between the part and the structure.

Abstract: Filling and leveling methods and apparatus for building tight tolerance surfaces are disclosed. An example method includes applying one or more of a tape or a sealant along an interior of a recess of a vehicle to move through a fluid. The example method includes leveling the one or more of the tape or the sealant to a first height at a first edge of the recess and a second height at a second edge of the recess to modify a fluid dynamic property of a fluid flow over the vehicle.

Abstract: A variable-width viscous fluid applicator, and related methods, may include an applicator having wall portions adjustable toward and away from each other, an injection port being formed in a bridge portion that spans upper ends of the wall portions. The applicator may be engaged around the edge of a component such as a panel. A bead of viscous fluid may be applied and shaped by injecting the fluid through the injection port and moving the applicator along the panel edge.

Abstract: A variable-width viscous fluid applicator, and related methods, may include an applicator having wall portions adjustable toward and away from each other, an injection port being formed in a bridge portion that spans upper ends of the wall portions. The applicator may be engaged around the edge of a component such as a panel. A bead of viscous fluid may be applied and shaped by injecting the fluid through the injection port and moving the applicator along the panel edge.

Abstract: Filling and leveling methods and apparatus for building tight tolerance surfaces are disclosed. An example method includes applying one or more of a tape or a sealant along an interior of a recess of a vehicle to move through a fluid. The example method includes leveling the one or more of the tape or the sealant to a first height at a first edge of the recess and a second height at a second edge of the recess to modify a fluid dynamic property of a fluid flow over the vehicle.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

Abstract: A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

Abstract: A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.