Abstract: A multi-chip package comprises a first die comprising a first integrated circuit and a second die comprising a second integrated circuit. A first plurality of contact pads disposed on the first die are coupled to the first integrated circuit, wherein the first plurality of contact pads comprises a first mode pad coupled to a first device formed on the first die. The first mode pad is coupled to a first potential and causes the first device to operate in a first mode. A second plurality of contact pads disposed on the second die are coupled to the second integrated circuit. The second plurality of contact pads comprises a second mode pad coupled to a second device formed on the second die. The second mode pad is coupled to a second potential and causes the second device to operate in a second mode. The first mode and the second mode are selected based on the relative position of the first die and the second die.

Abstract: Embodiments of the invention generally provide methods and apparatus for constructing multi chip packages having balance performance as between the various integrated circuits in a stack. In one embodiment, contacts on an outer surface of a first pad are “redistributed” from one area of the outer surface to another area of the first pad (e.g., to a different area of the outer surface). A second chip is adjacent to, and laterally offset with, the first chip, thereby exposing the redistributed contacts of the first chip.

Abstract: A multichip module (MCM) comprises a first integrated circuit and a second integrated circuit, a bridge layer over at least a portion of the second integrated circuit, one or more first interconnects conductively coupled between one or more contact areas of the first integrated circuit and one or more first contact areas of the bridge layer, and one or more second interconnects conductively coupled between one or more second contact areas of the bridge layer and one or more contact areas for a package. At least a portion of the first integrated circuit is positioned over a portion of the second integrated circuit. The bridge layer for one or more embodiments may define one or more signal paths between one or more first contact areas of the bridge layer and one or more second contact areas of the bridge layer.

Abstract: An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may be added to conventional pull-up and/or pull-down current paths to compensate for process variations by supplementing the current drive of transistors used to charge (PMOS) or discharge (NMOS) an output node of and end driver (e.g., inverter) stage of an OCD.

Abstract: A temperature compensated delay circuit for delaying a signal within an integrated circuit includes a temperature sensor. The temperature sensor is configured to sense a temperature proximal to the integrated circuit and configured to provide a control signal representative of the sensed temperature proximal to the integrated circuit. A delay chain is configured to receive a signal and provide a plurality of output signals. Each output signal has a time delay distinct from other output signals. A multiplexer is configured to receive the plurality of output signals from the delay chain and to receive the control signal from the temperature sensor representative of the sensed temperature. The multiplexer is configured to provide a temperature compensated delayed output signal.

Abstract: A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.