Patents by Inventor Thoi NGUYEN THE
Thoi NGUYEN THE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240064578Abstract: An operation for supporting a service in a wireless communication system. The operation may include receiving a request for a second service by a terminal/UE performing a first service in a first radio access technology (RAT), identifying at least one RAT capable of supporting the second service from a database including service support information in case that the first RAT is unable to perform the second service, performing handover to a second RAT included in the at least one RAT, and performing the second service in the second RAT.Type: ApplicationFiled: July 21, 2023Publication date: February 22, 2024Inventors: Hau TRUONG VAN, Nam TA PHUONG, Thinh NGUYEN VAN, Duc HOANG MINH, Thoi NGUYEN THE
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Publication number: 20210161356Abstract: A method and device for cleaning drinkware without using electricity are disclosed including a handle, a shaft connected to the handle, a cleaning brush connected to the shaft, and a top section connected to the cleaning brush; when the interior bottom of a drinkware is pressed down, creating a pressure upon the top section, the cleaning brush is rotated in a first direction, and when the pressure decreases, the cleaning brush rotates in a second direction opposite to the first direction.Type: ApplicationFiled: April 9, 2017Publication date: June 3, 2021Inventors: TOAN VAN LUU, Trung Thoi Nguyen
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Patent number: 8176339Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.Type: GrantFiled: August 17, 2007Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Gary Dean Anderson, Hoa Cong Nguyen, Thoi Nguyen
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Patent number: 7992023Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.Type: GrantFiled: December 20, 2007Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Gary Dean Anderson, Hoa Cong Nguyen, Thoi Nguyen
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Patent number: 7734444Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.Type: GrantFiled: November 9, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Ronald Xavier Arroyo, Kenneth A. Bird, William A. Ciarfella, Bret Peter Elison, Gary Franklin Goth, Terrance Wayne Kueper, Thoi Nguyen, Roger Donell Weekly
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Patent number: 7496772Abstract: In a computer system having a power supply, processor, and additional subcomponents that are powered by the power supply, a method for estimating the total power requirements of the system under a variety of operating modes and configurations. In an exemplary embodiment, information concerning power requirements for each subcomponent under its operating modes is stored within non-volatile memory within the subcomponents. This information is accessed by the processor during the boot sequence, and if the information is not available, substitute information is provided. The compiled information is tabulated to compute the estimated total power requirement of the current hardware configuration. A display of this information, along with configuration selection rules, enables the user to select alternative operating modes and configurations and to show the resulting estimated power requirements.Type: GrantFiled: March 4, 2008Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventor: Thoi Nguyen
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Publication number: 20080201710Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.Type: ApplicationFiled: August 17, 2007Publication date: August 21, 2008Inventors: Gary Dean Anderson, Hoa Cong Nguyen, Thoi Nguyen
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Publication number: 20080165490Abstract: A computer chassis is provided that may accommodate direct access storage device cages for various form factors. A 3.5-inch direct access storage device (DASD) cage may support 3.5-inch serial attached SCSI (SAS) direct access storage devices. The 3.5-inch SAS DASD cage includes a DASD backplane with a main connector and eight SAS drive connectors. A SFF direct access storage device cage may support SFF SAS direct access storage devices. The SFF SAS DASD cage may include a DASD backplane with a main connector and two port expanders. The port expanders may support up to twelve SAS DASD with redundant SAS channel wiring and one external 4-channel SAS port.Type: ApplicationFiled: January 9, 2007Publication date: July 10, 2008Inventors: Patrick A. Buckland, Ray C. Laning, Thoi Nguyen, Kenneth R. Peters, Edward J. Seminaro, Rebeccah J. Vossberg
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Publication number: 20080112456Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.Type: ApplicationFiled: November 9, 2007Publication date: May 15, 2008Inventors: Ronald Xavier Arroyo, Kenneth A. Bird, William A. Ciarfella, Bret Peter Elison, Gary Franklin Goth, Terrance Wayne Kueper, Thoi Nguyen, Roger Donell Weekly
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Publication number: 20080092137Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.Type: ApplicationFiled: December 20, 2007Publication date: April 17, 2008Inventors: Gary Anderson, Hoa Nguyen, Thoi Nguyen
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Patent number: 7346792Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.Type: GrantFiled: August 12, 2004Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Gary Dean Anderson, Hoa Cong Nguyen, Thoi Nguyen
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Patent number: 7338818Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.Type: GrantFiled: May 19, 2005Date of Patent: March 4, 2008Assignee: International Business Machines CorporationInventors: Ronald Xavier Arroyo, Kenneth A. Bird, William A. Ciarfella, Bret Peter Elison, Gary Franklin Goth, Terrance Wayne Kueper, Thoi Nguyen, Roger Donell Weekly
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Publication number: 20060263912Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.Type: ApplicationFiled: May 19, 2005Publication date: November 23, 2006Inventors: Ronald Arroyo, Kenneth Bird, William Ciarfella, Bret Elison, Gary Goth, Terrance Kueper, Thoi Nguyen, Roger Weekly
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Publication number: 20060036877Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.Type: ApplicationFiled: August 12, 2004Publication date: February 16, 2006Applicant: International Business Machines CorporationInventors: Gary Anderson, Hoa Nguyen, Thoi Nguyen
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Patent number: 6657325Abstract: A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e.g., a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan.Type: GrantFiled: January 11, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Robert Christopher Dixon, Thoi Nguyen
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Patent number: 6496911Abstract: An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.Type: GrantFiled: October 2, 1998Date of Patent: December 17, 2002Assignee: International Business Machines CorporationInventors: Robert Christopher Dixon, Thoi Nguyen, Tuan Hoang Nguyen
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Publication number: 20020088615Abstract: A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e.g., a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan. In another aspect of the present invention, an upgradeable fan circuit for use with a cooling system having a first fan that provides a tach feedback signal through a feedback connector is disclosed.Type: ApplicationFiled: January 11, 2001Publication date: July 11, 2002Applicant: International Business Machines CorporationInventors: Robert Christopher Dixon, Thoi Nguyen
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Patent number: 6223309Abstract: An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus.Type: GrantFiled: October 2, 1998Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Robert Christopher Dixon, Van Hoa Lee, Thoi Nguyen
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Patent number: 6115773Abstract: A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus.Type: GrantFiled: September 24, 1998Date of Patent: September 5, 2000Assignee: International Business Machines CorporationInventors: Louis Bennie Capps, Jr., Robert Christopher Dixon, Thoi Nguyen, Khuong Huu Pham
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Patent number: 6081862Abstract: A method and implementing system is provided which includes a switching device as part of a circuit board transmission line or trace serially connecting a plurality of device terminal sockets to a common node. When device terminals are left unconnected, corresponding segments of the connecting transmission line on the circuit board are disconnected to provide transmission line segments corresponding to the number of devices actually used. As a result, signal transition time for signals at the common node is optimized in accordance with the number of devices actually used.Type: GrantFiled: August 26, 1998Date of Patent: June 27, 2000Assignee: International Business Machines CorporationInventors: Robert Christopher Dixon, Thoi Nguyen