Abstract: A method and apparatus for detecting and identifying the attributes of level-2 (L2) memory cache modules in a computer system. An ID Module is attached to each L2 cache memory module containing memory attribute information such as size, presence or absence of parity, synchronous or asynchronous access ability, electrical timing, etc. The information is accessible using a parallel or serial interface.

Abstract: A connector on a printed circuit board of a computer system is reused to reduce a number of connectors utilized on a motherboard of a computer system. By recognizing that some signals are common between a programming application performed during a manufacturing process and a second application performed while the computer system is a normal customer operation, the connector may be used to provide data values during both the manufacturing process and normal customer operation. Stated another way, data signals used to drive programmed data during the manufacturing process may be re-used to provide serial data to an input/output device during normal customer operation.

Abstract: A method and apparatus for providing a memory system having error checking and correction (ECC) capability, and parity error detection capability on the same memory card, and user selection of either capability using the same type of memory modules. A memory controller having programmable configuration registers is provide for user selection of either ECC or parity capability. Eight-byte Dual in-line Memory Modules are used to provide 64-bit data which allows the memory controller to use eight extra bits for both ECC and parity capability.

Abstract: A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

Abstract: A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the data and a control logic for dividing a concurrent address and data bus transactions into an address bus transaction followed by a data bus transaction. During a read operation, the requesting device is forced to wait for data availability before entering the data bus transaction. During a write operation, the data bus transaction is delayed by using a storage mechanism that effectively separates the address transaction from the data transaction. The present invention also provides direct memory access fly-by operations between an input/output device and a memory device. These operations are accomplished by isolating a secondary bus from the system bus and allowing the destination device to capture the requested data as soon as it is available on the system bus.

Abstract: A wear-resistant ribbon guide surface (11 or 25a, 25b) is added to a thermal printhead (1) to lower the ribbon exit angle after printing or to shift the ribbon exit position away from the printing. The angle past that surface remains large enough for visibility of prior printing. The modification of exit conditions makes the printing darker and significantly improves printhead life.