Abstract: Polishing of a non-planar surface layer on a semiconductor substrate is conducted by providing an oxidized boron nitride polish stop layer on the semiconductor substrate, forming the non-planar surface layer on the oxidized boron nitride polish stop layer, the oxidized boron nitride polish stop layer being polish selective relative to the non-planar surface layer, and polishing the non-planar surface layer until the oxidized boron nitride polish stop layer is reached.

Abstract: A process of fabricating an electrical resistor and a product produced thereby in which trimming of a resistive element of a material exhibiting thermosetting properties is accomplished by in-situ annealing of one or more regions across the width of the resistive element to certain predetermined temperatures, thereby altering the crystal properties and the sheet resistance within those regions. Annealing is preferably done by laser radiation at levels below that at which any cutting or ablation of the resistive element will occur, thus avoiding defects in the resistor or associated circuits. By controlling laser radiation and the annealing process, virtually any desired trim slope may be obtained, resulting in improved trimming accuracy. Efficiency of the process is enhanced by annealing the resistive element to obtain compound trim slopes corresponding to coarse and fine trimming of the resistive element.

Abstract: Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching procedures to accommodate differences in stud elevation and in stud size, are features which provide substantial planarity in the successive levels.

Abstract: The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF.sub.4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.