Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Abstract: A fastening assembly is constituted by a plate-like member provided with a plurality of laterally extending projections which can be pushed into position between and then turned into engagement with respective slots formed in protrusions. In one aspect, at least one of the projections and/or at least one of the slots is adapted to give a wedging effect. In another aspect, the protrusions are located around an inner periphery of otherwise circular outline presented by a hollow member, and the projections are formed as arcuate sectors located around the plate-like member which presents an outer periphery of circular outline other than at recesses for receiving the respective protrusions.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 1010 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.

Abstract: An orbital disc sander support is provided which may support an active orbital disc sander in a stationary position so that an operator can attend to other tasks without having to de-activate the sander or worry that the sander will fall off of the work area. This both helps to protect the sander and increases operator efficiency by eliminating time wasted waiting for the orbital disc to reach its operating speed or to stop before continuing with the next task. The support has a turntable, which includes a platform rotatably mounted to a base, and may employ a retaining wall for retaining the sander. The base may be provided with a cushion to absorb vibrations and to prevent the base from slipping off the work area. Alternatively, the base may simply be secured to the work area. The platform may also be provided with a rubber pad to help clean the sanding disc surface of the orbital disc sander.

Abstract: The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO.sub.2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 10.sup.10 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.

Abstract: The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole. Microelectronic devices containing the micro-post wiring of the present invention are also disclosed herein.

Abstract: An automatic test apparatus for circuit boards in which the system is divided into an assembly sub-system, and a control sub-system. Probes are transferred from a magazine to a test head that is comprised of a base plate and probe plate along with associated support tables that enable X and Y translation of the probe plate to accommodate random pattern test points. The assembled test head is conveyed to a test station wherein a pressure plate contacts the circuit board being tested which in turn contacts the test head to carry out testing. The control sub-system covers control of all aspects of probe transfer including control of ejector members for probe transfer.