Abstract: Provided herein are cyclic polypeptide compounds that can, e.g., bind specifically to human proprotein convertase subtilisin/kexin type 9 (PCSK9) and optionally also inhibit interaction between human PCSK9 and human low density lipoprotein receptor (LDLR), and pharmaceutical compositions comprising one or more of these compounds. Also provided are methods of reducing LDL cholesterol level in a subject in need thereof that include administering to the subject one or more of the cyclic polypeptide compounds or a pharmaceutical composition provided herein.

Abstract: A download dispatch circuit initiates download of an input tile of an input feature map in response to a source buffer of two or more source buffers being available for the input tile, and indicates that the input tile is available in response to completion of the download. An operation dispatch circuit initiates a neural network operation on the input tile in response to the input tile being available and a first destination buffer of two or more destination buffers being available for an output tile of an output feature map, and indicates that the output tile is available in response to completion of the neural network operation. An upload dispatch circuit initiates upload of the output tile to the output feature map in response to the output tile being available, and indicates that the first destination buffer is available in response to completion of the upload.

Abstract: The embodiments herein describe techniques for monitoring guard bits in multi-result vectors generated by a first arithmetic unit in a chain and using side band logic to add or subtract offset values from guard bits in a second, subsequent arithmetic unit in the chain. In this manner, the guard bits can be adjusted on the fly (e.g., without interrupting or terminating the chain) to ensure the guard bits do not overflow. The side band logic can maintain a guard bits overflow value which is then combined with the output vector from the final arithmetic unit in the chain to compensate for adjusting the guard bits at the various arithmetic units in the chain. In this manner, the chain can have any desired length.

Abstract: The embodiments herein describe handling overflow that occurs between different portions of a multi-result vector storing results from performing multiple operations in parallel. Rather than using guard bits to separate the various results in the multi-result vector, the embodiments herein describe using overflow monitors to detect and account for overflow that can occur in a multi-result vector that is passed in a chain of arithmetic units. Side band logic evaluates the LSBs in the operands for the reduced-precision operations to generate an expected value of performing the operation and compares the expected value to an actual value of the corresponding bits in the multi-result vector. If the expected and actual values match, then there was no overflow. However, if the values do not match, the side band logic updates the overflow value so that this overflow can be corrected once the final multi-result vector has been calculated.

Abstract: A flash memory system having the capability of streaming data directly from flash memory to the interface of a host computer in order to substantially reduce latency of to-host transfers, while also maintaining the capabilities for caching and overlapped flash I/O provided by RAM DMA transfers. When data is read from the flash memory, the data is transferred into the RAM buffer and at the option of the memory controller, directly (via an intermediate FIFO) to the host interface. This results in a desirable reduction in the latency of data transfer because as soon as the first byte of data is read from the flash memory by the DMA engine, the data will be transferred directly to the host interface. Because the data is also being transferred to the buffer RAM, preferred embodiments of the present invention still provide the advantages of using an intermediate transfer buffer.